View source for DEC PRISM

{{Short description|RISC instruction set architecture}}
{{distinguish|Apollo PRISM}}
{{Infobox CPU architecture
| name        = DEC PRISM
| designer    = [[Digital Equipment Corporation]]
| bits        = [[32-bit]]
| introduced  = 1988 (cancelled)
| image       = Dec-prism.svg
| version     = 
| design      = [[Reduced instruction set computer|RISC]]
| type        = 
| encoding    = 
| branching   = 
| endianness  = 
| page size   = 
| extensions  = 
| open        = 
| predecessor = 
| successor   = [[DEC Alpha]]
| registers   =
*64× 32-bit general purpose registers
*16× 64-bit vector registers
}}

'''PRISM''' ('''P'''arallel '''R'''educed '''I'''nstruction '''S'''et '''M'''achine)<ref>{{cite web |title=Sketch of DEC PRISM |author=Mark Smotherman 
|url=https://people.cs.clemson.edu/~mark/prism.html
|quote=PRISM (Parallel Reduced Instruction Set Machine) ... first draft of PRISM architecture in August 1985; DEC cancels the project in 1988 in favor of a MIPS-based ...}}</ref> was a [[32-bit]] [[RISC]] [[instruction set architecture]] (ISA) developed by [[Digital Equipment Corporation]] (DEC). It was the outcome of a number of DEC research projects from the 1982–1985 time-frame, and the project was subject to continually changing requirements and planned uses that delayed its introduction. This process eventually decided to use the design for a new line of [[Unix workstation]]s.

The [[arithmetic logic unit]] (ALU) of the '''microPrism''' version had completed design in April 1988 and samples were fabricated, but the design of other components like the [[floating point unit]] (FPU) and [[memory management unit]] (MMU) were still not complete in the summer when DEC management decided to cancel the project in favor of [[MIPS Technologies|MIPS]]-based systems.<ref>{{cite web|url=http://www.bitsavers.org/pdf/dec/prism/memos/880617_PRISM_killed.pdf|date=1988-06-17|title=PRISM killed|access-date=2021-01-05|website=bitsavers.org}}</ref> An operating system codenamed [[DEC MICA|MICA]] was developed for the PRISM architecture, which was intended as a replacement for both [[OpenVMS|VAX/VMS]] and [[ULTRIX]] on PRISM, although a standalone PRISM ULTRIX port was eventually created when the original multi-personality goal of MICA proved infeasible.<ref>{{cite web|url=http://www.bitsavers.org/pdf/dec/prism/memos/880530_Cutler_PRISM_vs_MIPS.pdf|title=DECwest/SDT Agenda|author=Dave Cutler|date=1988-05-30|website=bitsavers.org}}</ref><ref>{{cite web| url=https://www.computerhistory.org/collections/catalog/102781228| title=DECWEST engineering : today, tomorrow, and the future, part 2 of 2| website=computerhistory.org| publisher=DEC| date=1988-04-20| access-date=2025-05-21}}</ref>

PRISM's cancellation had significant effects within DEC. Many of the team members left the company over the next year, notably [[Dave Cutler]] who moved to [[Microsoft]] and led the development of [[Windows NT]]. The MIPS-based workstations were moderately successful among DEC's existing [[Ultrix]] users but had little success competing against companies like [[Sun Microsystems]]. Meanwhile, DEC's cash-cow [[VAX]] line grew increasingly less performant as new RISC designs outperformed even the top-of-the-line [[VAX 9000]]. As the company explored the future of the VAX they concluded that a PRISM-like processor with a few additional changes could address all of these markets. Starting where PRISM left off, the [[DEC Alpha]] program started in 1989.

==History==
===Background===
Introduced in 1977, the [[VAX]] was a runaway success for DEC, cementing its place as the world's #2 computer vendor behind [[IBM]]. The VAX was noted for its rich [[instruction set architecture]] (ISA), which was implemented in complex [[microcode]]. The VMS [[operating system]] was layered on top of this ISA, which drove it to have certain requirements for [[interrupt]] handling and the memory model used for [[memory paging]]. By the early 1980s, VAX systems had become "the computing hub of many technology-driven companies, sending spokes of RS-232 cables out to a rim of VT-100 terminals that kept the science and engineering departments rolling."{{sfn|Comerford|1992|p=26}}

This happy situation was upset by the relentless improvement of [[semiconductor manufacturing]] as encoded by [[Moore's Law]]; by the early 1980s there were a number of capable [[32-bit]] single-chip [[microprocessor]]s with performance similar to early VAX machines yet able to fit into a desktop [[pizza box form factor]]. Companies like [[Sun Microsystems]] introduced [[Motorola 68000 series]]-based [[Unix workstation]]s that could replace a huge multi-user VAX machine with one that provided even more performance but was inexpensive enough to be purchased for every user that required one. While DEC's own microprocessor teams were introducing a series of VAX implementations at lower price-points, the [[price-performance ratio]] of their systems continued to be eroded. By the later half of the 1980s, DEC found itself being locked out of the technical market.{{sfn|Comerford|1992|p=26}}

===RISC===
During the 1970s, [[IBM]] had been carrying out studies of the performance of their computer systems and found, to their surprise, that 80% of the computer's time was spent performing only five operations. The hundreds of other instructions in their ISAs, implemented using microcode, went almost entirely unused. The presence of the microcode introduced a delay when the instructions were decoded, so even when one called one of those five instructions directly, it ran slower than it could if there was no microcode. This led to the [[IBM 801]] design, the first modern [[RISC]] processor.<ref>{{Cite journal | last1 = Cocke | first1 = John | last2 = Markstein | first2 = Victoria | doi = 10.1147/rd.341.0004 | url = https://www.cis.upenn.edu/~milom/cis501-Fall11/papers/cocke-RISC.pdf | title = The evolution of RISC technology at IBM | journal = IBM Journal of Research and Development | volume = 34 | issue = 1 | pages = 4–11 | date = January 1990 | access-date = 2022-10-05}}</ref>

Around the same time, in 1979, [[David Patterson (computer scientist)|Dave Patterson]] was sent on a [[sabbatical]] from [[University of California, Berkeley]] to help DEC's west-coast team improve the VAX microcode. Patterson was struck by the complexity of the coding process and concluded it was untenable. He first wrote a paper on ways to improve microcoding, but later changed his mind and decided microcode itself was the problem. He soon started the [[Berkeley RISC]] project.<ref>{{cite web |website=AM SIGARCH |date=30 May 2018 |first=David |last=Patterson |title=RISCy History |url=https://www.sigarch.org/riscy-history/}}</ref> The emergence of RISC sparked off a long-running debate within the computer industry about its merits; when Patterson first outlined his arguments for the concept in 1980, a dismissive dissenting opinion was published by DEC,<ref>{{cite web |url= http://www-inst.cs.berkeley.edu/~n252/paper/RISC-clark.pdf |archive-url=https://web.archive.org/web/20190418165128/http://www-inst.cs.berkeley.edu/~n252/paper/RISC-clark.pdf |archive-date=18 April 2019 |title=Comments on "The Case for the Reduced Instruction Set Computer," by Patterson and Ditzel |first1=Douglas  |last1=Clark |first2=William |last2=Streck |date=September 1980}}</ref> but by the mid-1980s the consensus at DEC was that RISC was at least twice as efficient as CISC. The company had two options: Improve VAX as much as possible until the limitation of its 32-bit address space forced a replacement around 1999, or develop RISC as fast as possible.<ref name="dtj1990spring_decstation3100">{{ cite journal | url=http://www.bitsavers.org/pdf/dec/dtj/dtj_v02-02_1990.pdf | first1=Thomas C. | last1=Furlong | first2=Michael J. K. | last2=Nielsen | first3=Neil C. | last3=Wilhelm | title=Development of the DECstation 3100 | journal=Digital Technical Journal | volume=2 | issue=2 | date=Spring 1990 | publisher=Digital Equipment Corporation }}</ref><ref name="bellstreckerpdp11vaxalpha">{{Cite report |url=https://archive.computerhistory.org/resources/text/DEC/alpha/dec.alpha.bell_stecker.pdp-11_vax_and_alpha.1998.102630388.pdf |title=What Have We Learned from the PDP-11 - What We Have Learned from VAX and Alpha |last1=Bell |first1=Gordon |author-link1=Gordon Bell |last2=Strecker |first2=W.D. |access-date=2025-06-26}}</ref>

By the mid-1980s practically every company with a processor design arm began exploring the RISC approach. Despite official disinterest,<ref>{{cite web |url= http://www-inst.cs.berkeley.edu/~n252/paper/RISC-clark.pdf |archive-url=https://web.archive.org/web/20190418165128/http://www-inst.cs.berkeley.edu/~n252/paper/RISC-clark.pdf |archive-date=18 April 2019 |title=Comments on "The Case for the Reduced Instruction Set Computer," by Patterson and Ditzel |first1=Douglas  |last1=Clark |first2=William |last2=Streck |date=September 1980}}</ref> DEC was no exception. In the period from 1982 to 1985, no fewer than four attempts were made to create a RISC chip at different DEC divisions. '''Titan''' from DEC's Western Research Laboratory (WRL) in [[Palo Alto, California]] was a high-performance [[Emitter-coupled logic|ECL]] based design that started in April 1982, intended to run [[Unix]], and achieving this objective in December 1985.<ref name="titan1988">{{ cite book | url=https://archive.org/details/bitsavers_dectechrep_207144/page/n2/mode/1up | title=Titan System Manual | publisher=Digital Equipment Corporation | date=2 August 1988 | access-date=7 August 2025 | pages=2 }}</ref> Titan ran a modified version of Ultrix called Tunix (Titan Unix) with rewritten process and memory management functions.<ref name="dec-wrl-89-14">{{ cite tech report | url=https://archive.org/details/bitsavers_dectechrep_436158/page/n6/mode/1up | title=Long Address Traces from RISC Machines: Generation and Analysis | publisher=Digital Equipment Corporation | last1=Borg | first1=Anita | last2=Kessler | first2=R. E. | last3=Lazana | first3=Georgia | last4=Wall | first4=David W. | date=September 1989 | access-date=7 August 2025 | pages=3 }}</ref> The continuing performance gulf between the servers at WRL, which included these RISC-based Titan servers, and the VAX-based workstations being used as clients would eventually precipitate the development of the MIPS-based DECstation.{{r|dtj1990spring_decstation3100}}

Titan was accompanied by the MultiTitan project, running from mid-1984 until January 1988 which explored instruction-level parallelism, shared memory multiprocessing, explicit cache management, high-performance floating-point arithmetic, unified scalar and vector processing, and the use of a "software definition" for the architecture.<ref name="dec-wrl-87-8">{{ cite tech report | url=https://archive.org/details/bitsavers_dectechrep_262179/mode/2up | title=MultiTitan: Four Architecture Papers | publisher=Digital Equipment Corporation | date=5 April 1988 | access-date=12 August 2025 | pages=1–4 }}</ref> In April 1988, this effort delivered samples of a microprocessor fabricated using a CMOS process that were tested within the existing Titan architecture, able to operate at frequencies up to between 70&nbsp;MHz and 90&nbsp;MHz depending on the individual part, but falling short of the desired 100&nbsp;MHz. Without the accompanying floating-point and cache management chips, benchmarking could not be performed, with only estimates of 20&nbsp;MIPS performance being made.<ref name="dec-wrl-89-11">{{ cite book | url=https://archive.org/details/bitsavers_dectechrep_367962/mode/2up | title=A 20-MIPS Sustained 32-bit CMOS Microprocessor with High Ratio of Sustained to Peak Performance | publisher=Digital Equipment Corporation | last1=Jouppi | first1=Norman P. | last2=Tang | first2=Jeffrey Y. F. | date=July 1989 | access-date=12 August 2025 | pages=19 }}</ref>

'''SAFE''' (''Streamlined Architecture for Fast Execution'') was a [[64-bit]] design that started in 1982, designed by [[Alan Kotok]] (of [[Spacewar!]] fame) and Dave Orbits and intended to run VMS. '''HR-32''' (''Hudson, RISC, 32-bit'') started in 1984 by Rich Witek and [[Dan Dobberpuhl]] at the [[Hudson, MA]] fab, intended to be used as a [[Coprocessor|co-processor]] in [[VAX]] machine. The same year [[Dave Cutler]] started the '''CASCADE''' project at DECwest in Bellevue, Washington.{{sfn|Supnik|2008}}

===PRISM===
DEC used the large profits from VAX to fund the multiple competing projects, which caused delays and uncertainty.{{r|bellstreckerpdp11vaxalpha}} Eventually, Cutler was asked to define a single RISC project in 1985, selecting Rich Witek as the chief architect. In August 1985 the first draft of a high-level design was delivered, and work began on the detailed design. The PRISM specification was developed over a period of many months by a five-person team: Dave Cutler, Dave Orbits, Rich Witek, Dileep Bhandarkar, and Wayne Cardoza. Through this early period, there were constant changes in the design as debates within the company argued over whether it should be 32- or 64-bit, aimed at a commercial or technical workload, and so forth.{{sfn|Supnik|2008}}

These constant changes meant the final ISA specification was not complete until September 1986. At the time, the decision was made to produce two versions of the basic concept, DECwest worked on a "high-end" [[Emitter coupled logic|ECL]] implementation known as '''Crystal''', while the Semiconductor Advanced Development team worked on '''microPRISM''', a [[CMOS]] version. This work was 98% done by 1985–86 and was heavily supported by simulations by Pete Benoit on a large [[VAXcluster]].{{sfn|Supnik|2008}}

Through this era there was still considerable scepticism on the part of DEC engineering as a whole about whether RISC was really faster, or simply faster on the trivial five-line programs being used to demonstrate its performance.  Based on the Crystal design, in 1986 it was compared to the then-fastest machine in development, the [[VAX 8800]]. The conclusion was clear: for any given amount of investment, the RISC designs would outperform a VAX by 2-to-1.{{sfn|Schein|2003|p=209}}

In the middle of 1987, the decision was made that both designs be 64-bit, although this lasted only a few weeks. In October 1987, Sun introduced the [[Sun-4]]. Powered by a 16&nbsp;MHz [[SPARC]], a commercial version of Patterson's RISC design, it ran four times as fast as their previous top-end Sun-3 using a 20&nbsp;MHz [[Motorola 68020]]. With this release, DEC once again changed the target for PRISM, aiming it solely at the workstation space. This resulted in the microPRISM being respecified as a 32-bit system while the Crystal project was canceled. This introduced more delays, putting the project far behind schedule.{{sfn|Supnik|2008}} 

By early 1988 the system was still not complete; the CPU design was nearly complete, but the FPU and MMU, both based on the contemporary [[Rigel (microprocessor)|Rigel chipset]] for the VAX, were still being designed.{{sfn|Supnik|2008}} The team decided to stop work on those parts of the design and focus entirely on the CPU. Design was completed in March 1988 and [[taped out]] by April.{{sfn|Supnik|2008}}

===Cancellation===
Throughout the PRISM period, DEC was involved in a major debate over the future direction of the company. As newer RISC-based workstations were introduced, the performance benefit of the VAX was constantly eroded, and the [[price/performance ratio]] completely undermined. Different groups within the company debated how to best respond. Some advocated moving the VAX into the high-end, abandoning the low-end to the workstation vendors like Sun. This led to the [[VAX 9000]] program, which was referred to internally as the "IBM killer". Others suggested moving into the workstation market using PRISM or a commodity processor. Still others suggested re-implementing the VAX on a RISC processor.{{sfn|Supnik|2008}}

Frustrated with the growing number of losses to cheaper faster competitive machines, independently, a small [[skunkworks project|skunkworks]] group in [[Palo Alto]], outside of Central Engineering, focused on workstations and UNIX/[[Ultrix]], entertained the idea of using an off-the-shelf RISC processor to build a new family of workstations.  The group carried out due diligence, eventually choosing the [[R2000 (microprocessor)|MIPS R2000]]. This group acquired a development machine and prototyped a port of Ultrix to the system. From the initial meetings with MIPS to a prototype machine took only 90 days. Full production of a DEC version could begin as early as  January 1989, whereas it would be at least another year before a PRISM based machine would be ready.{{sfn|Supnik|2008}}

When the matter was raised at DEC headquarters the company was split on which approach was better. Bob Supnik was asked to consider the issue for an upcoming project review. He concluded that while the PRISM system appeared to be faster, the MIPS approach would be less expensive and much earlier to market. At the acrimonious review meeting by the company's Executive Committee in July 1988, the company decided to cancel Prism, and continue with the MIPS workstations and high-end VAX products. The workstation emerged as the [[DECstation 3100]].{{r|dtj1990spring_decstation3100}}{{sfn|Supnik|2008}}

By this time samples of the microPRISM had been returned and were found to be mostly working. They also proved capable of running at speeds of 50 to 80&nbsp;MHz, compared to the R2000's 16 to 20. Performance predictions based on these observations suggested a significant performance improvement over existing and announced RISC products from other vendors. However, without the accompanying floating-point unit, whose design had been halted, or the cache interface chip required for operating at such frequencies, which had been part of a cancelled project, floating-point performance predictions remained hypothetical.<ref name="digital19881021_uprism">{{ cite tech report | url=http://bitsavers.org/pdf/dec/prism/memos/881021_uPRISM_charcterization.pdf | title=uPRISM - The Final Chapter | publisher=Digital Equipment Corporation | date=21 October 1988 | access-date=17 February 2024 }}</ref>

===Legacy===
By the time of the July 1988 meeting, the company had swung almost entirely into the position that the RISC approach was a workstation play. But PRISM's performance was similar to that of the latest VAX machines and the RISC concept had considerable room for growth. As the meeting broke up, [[Ken Olsen]] asked Supnik to investigate ways that Digital could keep the performance of VMS systems competitive with RISC-based Unix systems.<ref name="supnik-alpha">{{cite web |url=http://simh.trailing-edge.com/semi/ev4.html|title=EV-4 (1992)|date=2008-02-24}}</ref>

A group of engineers formed a team, variously referred to as the "RISCy VAX" or "Extended VAX" (EVAX) task force, to explore this issue.<ref name="supnik-alpha" /> By late summer, the group had explored three concepts, a subset of the VAX ISA with a RISC-like core, a translated VAX that ran native VAX code and translated it on-the-fly to RISC code and stored in a cache, and the ultrapipelined VAX, a much higher-performance CISC implementation. All of these approaches had issues that meant they would not be competitive with a simple RISC machine.{{sfn|Comerford|1992|p=28}}

The group next considered systems that combined both an existing VAX single-chip solution as well as a RISC chip for performance needs. These studies suggested that the system would inevitably be hamstrung by the lower-performance part and would offer no compelling advantage.{{sfn|Comerford|1992|p=28}}

It was at this point that Nancy Kronenberg pointed out that people ran VMS, not VAX, and that VMS only had a few hardware dependencies based on its modelling of interrupts and memory paging. There appeared to be no compelling reason why VMS could not be ported to a RISC chip as long as these small bits of the model were preserved. Further work on this concept suggested this was a workable approach.{{sfn|Comerford|1992|p=28}}

Supnik took the resulting report to the Strategy Task Force in February 1989. Two questions were raised: could the resulting RISC design also be a performance leader in the Unix market, and should the machine be an open standard? And with that, the decision was made to adopt the PRISM architecture with the appropriate modifications, eventually becoming the [[DEC Alpha|Alpha]], and began [[OpenVMS#Port to Alpha|the port of VMS to the new architecture]].<ref>{{cite web|url=https://dspace.mit.edu/bitstream/handle/1721.1/48380/managingtechnolo00katz.pdf|date=April 1993|title=Managing Technological Leaps: A study of DEC's Alpha Design Team}}</ref>

When PRISM and MICA were cancelled, Dave Cutler left Digital for [[Microsoft]], where he was put in charge of the development of what became known as [[Windows NT]]. Cutler's architecture for NT was heavily inspired by many aspects of MICA.<ref>{{cite book |last1=Zachary |first1=G. Pascal |title=Showstopper!: The Breakneck Race to Create Windows NT and the Next Generation at Microsoft |date=2014 |publisher=Open Road Media |isbn=978-1-4804-9484-8 |url=https://books.google.com/books?id=o2IkAwAAQBAJ&q=%22Dave+Cutler%22+march+13&pg=PT9 |access-date=2021-01-04|language=en}}</ref><ref>{{cite web|url=http://neilrieck.net/docs/dave_cutler-prism-mica-emerald-etc.html|title=Dave Cutler, PRISM, Mica, Emerald, etc.|author=Neil Rieck|website=neilrieck.net|access-date=2021-01-04}}</ref><ref>{{cite web|url=https://www.itprotoday.com/compute-engines/windows-nt-and-vms-rest-story|title=Windows NT and VMS: The Rest of the Story|author=Mark Russinovich|date=1998-10-30|access-date=2021-01-04|website=itprotoday.com}}</ref>

==Design==

In terms of [[integer]] operations, the PRISM architecture was similar to the [[MIPS Technologies|MIPS]] designs. Of the 32-bits in the [[instruction (computer science)|instruction]]s, the 6 highest and 5 lowest [[bit]]s were the instruction, leaving the other 21 bits of the word for encoding either a [[constant (programming)|constant]] or [[Processor register|register]] locations. Sixty-four 32-bit registers were included, as opposed to thirty-two in the MIPS, but usage was otherwise similar. PRISM and MIPS both lack the [[register window]]s that were a hallmark of the other major RISC design, Berkeley RISC.

The PRISM design was notable for several aspects of its [[instruction set]]. Notably, PRISM included '''Epicode''' (''extended processor instruction code''), which defined a number of "special" instructions intended to offer the [[operating system]] a stable [[Application Binary Interface|ABI]] across multiple implementations. Epicode was given its own set of 22 32-bit registers to use. A set of [[vector processor|vector processing]] instructions were later added as well, supported by an additional sixteen 64-bit vector registers that could be used in a variety of ways.

==References==
{{Reflist}}

===Bibliography===
* {{cite journal
 |first=Richard |last=Comerford
 |title= How DEC developed Alpha
 |journal=IEEE Spectrum
 |date=July 1992
 |volume=29
 |issue=7
 |pages=26–31
 |doi=10.1109/6.144508
 }}
* {{cite book
 |first=Edgar |last=Schein
 |title= DEC is dead, long live DEC
 |publisher= Berrett-Koehler
 |date=2003
 |isbn=9781576752258
 |url=https://books.google.com/books?id=gJRFXz8v0fMC
}}
* {{cite web
 |first= Bob |last=Supnik
 |url=http://simh.trailing-edge.com/semi/uprism.html 
 |title=MicroPrism
 |date= 24 February 2008 
|website= The Computer History Simulation Project 
}}

* Prism documents at [http://bitsavers.org/pdf/dec/prism bitsavers.org]

==Further reading==
* Bhandarkar, Dileep P. (1995). ''Alpha Architecture and Implementations''. Digital Press.
* Bhandarkar, D. et al. (1990. [https://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=63667 "High performance issue orientated architecture"]. ''Proceedings of Compcon Spring '90'', pp.&nbsp;153&ndash;160.
* Conrad, R. et al. (1989). [https://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=48185 "A 50 MIPS (peak) 32/64 b microprocessor"]. ''ISSCC Digest of Technical Papers'', pp.&nbsp;76&ndash;77.

{{Digital Equipment Corporation}}
{{RISC-based processor architectures}}
{{CPU technologies}}

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