View source for DEC 3000 AXP

{{Short description|Series of computer workstations and servers}}
{{no footnotes|date=September 2016}}
[[Image:sandpiper45.jpg|thumb|280px|DEC 3000 Model 700 Server]]

'''DEC 3000 AXP''' was the name given to a series of [[computer workstation]]s and [[server (computing)|server]]s, produced from 1992 to around 1995 by [[Digital Equipment Corporation]]. The DEC 3000 AXP series formed part of the first generation of computer systems based on the 64-bit [[Alpha AXP]] architecture. Supported [[operating system]]s for the DEC 3000 AXP series were DEC OSF/1 AXP (later renamed [[Digital UNIX]]) and OpenVMS AXP (later renamed [[OpenVMS]]).

All DEC 3000 AXP models used the [[Alpha 21064|DECchip 21064]] (EV4) or [[Alpha 21064|DECchip 21064A]] (EV45) processor and inherited various features from the earlier [[MIPS architecture]]-based [[DECstation]] models, such as the [[TURBOchannel]] bus and the I/O subsystem.

The DEC 3000 AXP series was superseded in late 1994, with workstation models replaced by the [[AlphaStation]] line and server models replaced by the [[AlphaServer]] line.

== Models ==
There were three DEC 3000 model families, codenamed [[Pelican]], [[Sandpiper]], and [[Flamingo]]. Within Digital, this led to the DEC 3000 series being affectionately referred to as "the seabirds".

{| class="wikitable" style="text-align: center;"
! width="100" | Model
! width="100" | Codename
! width="50"  | CPU
! width="80"  | CPU MHz
! width="100" | B-cache (L2)
! width="80"  | Chassis
! width="100" | Introduced
! width="100" | Withdrawn
|-
| '''Model 300'''
| Pelican
| EV4
| 150
| 256 [[Kilobytes|KB]]
| Desktop
| 1993-04-20{{Citation needed|date=October 2013}}
| ?
|-
| '''Model 300L'''
| Pelica
| EV4
| 100
| 256 KB
| Desktop
| 1993-04-20{{Citation needed|date=October 2013}}
| 1994-03-25
|-
| '''Model 300X'''
| Pelican+
| EV4
| 175
| 256 KB
| Desktop
| 1994-02-08
| 1995-10-02
|-
| '''Model 300LX'''
| Pelica+
| EV4
| 125
| 256 KB
| Desktop
| 1994-02-08
| 1995-06-23
|-
| '''Model 400'''
| Sandpiper
| EV4
| 133
| 512 KB
| Desktop
| 1992-11<ref name="wilson19921116">{{Cite magazine |last=Wilson |first=Jayne |date=1992-11-16 |title=DEC debuts its long-awaited 64-bit Alpha systems |url=https://books.google.com/books?id=N1EEAAAAMBAJ&pg=PA33#v=onepage |access-date=2025-06-30 |magazine=InfoWorld |page=33 |volume=14 |issue=46}}</ref>
| ?
|-
| '''Model 500'''
| Flamingo
| EV4
| 150
| 512 KB
| Pedestal
| 1992-11{{r|wilson19921116}}
| ?
|-
| '''Model 500X'''
| Hot Pink
| EV4
| 200
| 512 KB
| Pedestal
| 1993-04-20{{Citation needed|date=October 2013}}
| ?
|-
| '''Model 600'''
| Sandpiper+
| EV4
| 175
| 2 [[Megabytes|MB]]
| Desktop
| 1993-10-13
| 1995-10-02
|-
| '''Model 700'''
| Sandpiper45
| EV45
| 225
| 2 MB
| Desktop
| 1994-07-21{{Citation needed|date=October 2013}}
| 1995-10-02
|-
| '''Model 800'''
| Flamingo II
| EV4
| 200
| 2 MB
| Pedestal
| 1993-10-13
| 1994-02-12
|-
| '''Model 900'''
| Flamingo 45
| EV45
| 275
| 2 MB
| Pedestal
| 1994-07-21{{Citation needed|date=October 2013}}
| 1995-10-02
|-
|} 

'''Note:''' Server configurations of the Model 400/500/600/700/800/900 systems were suffixed with "S".

== Description ==

The logic in Flamingo- and Sandpiper-based systems are contained on two modules ([[printed circuit board]]s), the CPU module and the I/O module, with the CPU module being the largest board. The two modules are connected via a 210-pin connector. The logic in Pelican-based systems are contained the CPU module and system module. The CPU module is a daughterboard that plugs into the system module and contains the CPU and the B-cache (L2 cache).

The architecture of the Flamingo- and Sandpiper-based systems is based around a [[crossbar switch]] implemented by an ADDR (Address) ASIC, four SLICE (data slice) ASICs and a TC (TURBOchannel) ASIC. These ASICs connect the various different width buses used in the system, allowing data to be transferred to the different subsystems. [[Programmable Array Logic|PAL]]s were used to implement the control logic. The cache, memory and TURBOchannel controllers, as well as other control logic, is entirely implemented by PALs. Pelican-based systems have an entirely different architecture from the other systems, similar to that of late-model [[DECstation|Personal DECstations]] that they are based on, with a traditional workstation architecture with buses and buffers.

=== Memory ===

The Sandpiper and Flamingo used proprietary 100-pin, 40-bit (32 bits plus 8 bits ECC) [[Dynamic random access memory#Fast Page Mode DRAM (FPM)|Fast Page Mode]] [[SIMM]]s with capacities of 2&nbsp;MB, 4&nbsp;MB, 8&nbsp;MB, 16&nbsp;MB or 32&nbsp;MB.<ref>When applied to computer memory (RAM or cache) the quantities KB, MB and GB are defined as:
*1 B  = 8    [[bit|b]]
*1 KB = 1024 [[byte|B]]
*1 MB = 1024 [[kilobyte|KB]]
*1 GB = 1024 [[megabyte|MB]],
consistent with the [[JEDEC memory standards|JEDEC memory standard]].</ref> These were eight-way interleaved, providing a 256-bit-wide bus to memory. The Sandpiper had two such eight-SIMM banks, for up to 512 MB total system RAM, while the Flamingo had four banks and supported up to 1 GB. In comparison, the Pelican was a budget architecture utilising eight standard 72-pin Fast Page Mode SIMMs that were protected with longword parity instead of ECC, with capacities of 8&nbsp;MB or <!-- Yes, 16 MB and other double-sided SIMMs were not supported and did not function. --> 32&nbsp;MB, for a total of up to 256&nbsp;MB RAM. These were two-way interleaved, for a 64-bit-wide bus to memory.

=== Expansion slots ===

The DEC 3000 AXP series uses the 32-bit [[TURBOchannel]] [[bus (computing)|bus]] running at various speeds, 12.5&nbsp;MHz in the 300 models, 22.5&nbsp;MHz in the 400 models and 25&nbsp;MHz in models 500 to 900. The TURBOchannel bus is provided by an [[ASIC]], which connected it to the SLICE data path ASICs. The number to expansion slots also varied, the 300 models had two slots, except for the 300L, which had none. Models 400, 600 and 700 had three slots, the model 500X featured five, while models 500, 800 and 900 featured six.

=== Graphics ===

The Model 300 Series and the Model 500, 500S and 500X feature integrated graphics provided by the CXTurbo subsystem, which resides on the system module. This subsystem is essentially an onboard HX TURBOchannel option module. The subsystem features a SFB (smart [[frame buffer]]) ASIC, a [[Brooktree]] Bt459 [[RAMDAC]], 2 MB of [[VRAM]] and in the Model 500, 500S and 500X, a 256 KB [[Flash memory|flash]] ROM that holds part of the system firmware. The CXTurbo subsystem can reach resolutions of 1280 × 1024 at 72&nbsp;Hz in the 300, 300X and 300LX models, 1024 × 768 at 72&nbsp;Hz in the Model 300L and 1280 × 1024 at 66&nbsp;Hz or 72&nbsp;Hz in the Model 500, 500S and 500X.

Because of the DEC 3000 AXP's similarity with Digital's previous RISC workstation line, the [[DECstation]], the same TURBOchannel [[DECstation#Graphics|graphics options]], which consisted of framebuffers, 2D and 3D accelerated graphics, were carried over the DEC 3000 AXP. Like the DECstation, up to three (the actual number may be less, depending on the number of TURBOchannel option slots the system features) framebuffers of the same model can be installed in a single system to support [[Multi-monitor|multiscreen]] configurations.

Despite using the same graphics options as the DECstation at introduction, later options for the DEC 3000 AXP were designed exclusively for the platform. These options were Digital's ZLX-E1/E2/E3, ZLX-L1/L2 and ZLX-M1/M2 series of PixelVision architecture-based 2D/3D accelerated graphics and [[Ardent Computer Corporation|Kubota's]] high-end 3D accelerated graphics subsystem, the [[Ardent Computer Corporation|Denali]]. The Denali is an external enclosure that contains up to six [[Geometry pipeline|geometry engines]] and multiple memory modules. It was capable of advanced (for the time) 3D graphics, such as interactive [[volume rendering]]. It connects to the DEC 3000 AXP via a cable and a TURBOchannel interface module.

=== I/O subsystem ===

The I/O subsystem provides the DEC 3000 AXP with [[Ethernet]], [[ISDN]] and audio capability, four serial lines, and a [[real-time clock]]. The I/O subsystem is interfaced to TURBOchannel by the IOCTL ASIC, which also implements two 8-bit buses, known as IOBUS HI and IOBUS LO, to which the I/O devices connect to. These two 8-bit buses can be combined to serve as one 16-bit bus to provide an I/O device with more bandwidth. Ethernet is provided by an [[AMD]] [[AMD Lance Am7990|Am7990 LANCE]] (Local Area Network Controller for Ethernet), an AMD Am7992 SIA (Serial Interface Adapter) that implements the 10BASE-T or AUI Ethernet interface, and an ESAR (Ethernet Station Address ROM) that stores the MAC address. The Am7990 is the only I/O device in the subsystem to have a 16-bit interface to the IOCTL ASIC. ISDN and telephone-quality audio is provided by an AMD Am79C30A DSC (Digital Subscriber Controller). The four serial lines are provided by two [[Zilog]] Z85C30 SCC (Serial Communications Controller) dual [[UART]]s, and the real-time clock is a [[Dallas Semiconductor]] DS1287A.

=== SCSI interface ===

The DEC 3000 AXP used a TCDS (TURBOchannel Dual SCSI) ASIC to provide an interface between the [[SCSI]] controllers and the TURBOchannel bus. Early systems used one (Model 300s) or two (Model 400 and 500) [[NCR Corporation|NCR]] [[NCR 53C9x|53C94]] SCSI controllers, which provided one or two 5 MB/s<ref>When applied to parallel data transfer, the unit MB is defined as
1 MB = 1,000,000 B, 
so that 1 MB/s = 1,000,000 bytes per second.</ref> 8-bit single ended SCSI buses. Later and higher end systems such as the Model 600, 700, 800 and 900 also feature two SCSI controllers, but used the NCR 53CF94-2 instead, which provided faster 10 MB/s 8-bit single ended SCSI buses.

== Notes==

{{reflist}}

== References ==
* [https://web.archive.org/web/20110929020934/http://h18002.www1.hp.com/alphaserver/download/dec3000_ug.pdf DEC 3000 600/600S/700 AXP Owner's Guide]
* [http://paleoferrosaurus.com/documents/Alpha_Server_AXP/d3syspmb.pdf DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual, EK-D3SYS-PM.B01, July 1994, Digital Equipment Corporation]

== External links ==
*[http://www.pghardy.net/paul/programs/vms_cpus.html Paul Hardy's VMS CPU Model Summary]
*[http://www.hpl.hp.com/hpjournal/dtj/vol4num4/vol4num4art4.pdf Dutton,  Todd A., Eiref, Daniel, Kurth, Hugh R., Reisert, James J., and  Stewart, Robin L. (1992), "The Design of the DEC 3000 AXP Systems, Two High-performance Workstations", ''Digital Technical Journal'' '''4'''(4).]

{{DEC hardware}}

[[Category:DEC computers|3000 AXP]]
[[Category:DEC workstations|3000 AXP]]
[[Category:Computer-related introductions in 1992]]
[[Category:64-bit computers]]