View source for Cyrix 6x86

{{short description|Microprocessor}}
{{Use mdy dates|date=October 2020}}{{Infobox CPU
|name           = 6x86/MII
|image          = Cyrix 6x86-P166.jpg
|image_size     = 200px
|caption        = A Cyrix 6x86-P166 processor
|produced-start ={{plainlist|
*6x86 - Oct 1995
*6x86L - Jan 1997
*6x86MX - Jun 1997
*MII - May 1998
}} 
|produced-end   ={{plainlist|
*6x86 - Jun 1999
*6x86L - Jun 1999
*6x86MX - May 1998
*MII - Early 2000s
}} 
|model          = 
|transistors    = 4.3M 500 [[nanometers|nm]]
|slowest        =80 
|fastest        =333 
|fsb-slowest    =40 
|fsb-fastest    =100 
|soldby         ={{plainlist|
*[[Cyrix]]
*[[IBM]]
*[[SGS-Thomson]]
*[[VIA Technologies|VIA]]
}} 
|sock1          = [[Socket 7]]
|sock2          = [[Super Socket 7]]
|brand1         = 
|arch           = [[x86-16]], [[IA-32]]
|microarch      = 6x86
|cpuid          =
|code           = 
|numcores       = 1
|l1cache        = {{plainlist|
*16&nbsp;KB (6x86/L)
*64&nbsp;KB (6x86MX / MII)
}}
|application    = Desktop
|predecessor    = [[Cyrix 5x86]]
|successor      =[[Cyrix III]] 
|fast-unit=MHz|slow-unit=MHz|fsb-slow-unit=MHz|fsb-fast-unit=MHz|variant1=6x86, 6x86L, 6x86MX|manuf1=[[IBM]]|manuf2=[[SGS-Thomson]]|manuf3=[[National Semiconductor]]|core1=M1|core2=M1L (Low voltage)|core3=M1R (3M to 5M)|core4=MII (MMX)}}

The '''Cyrix 6x86''' is a line of fifth and sixth-generation, [[32-bit]] [[x86]] [[microprocessor]]s designed and released by [[Cyrix]] in 1995. Cyrix, being a [[Fabless manufacturing|fabless]] company, had the chips manufactured by [[IBM]] and [[SGS-Thomson]].<ref>{{Cite news |last=Slater |first=Michael |date=28 May 1996 |title=Beyond the Pentium; Intel's top challengers have reached the Pentium level, but do they pose a threat to the king of the CPU hill? We examine the chips and vendors to find out. |volume=15 |pages=100–102 |work=[[PC Mag]] |publisher=Ziff Davis, Inc. |issue=10 |url=https://books.google.com/books?id=MPfwx4yZJTQC&dq=cyrix+6x86&pg=PA102 |access-date=30 March 2022 |issn=0888-8507}}</ref><ref name=":0">{{Cite news |date=9 October 1995 |title=CYRIX CLAIMS ITS 100MHZ 6X86 CLONE IS THE FASTEST |work=[[TechMonitor]] |url=https://techmonitor.ai/technology/cyrix_claims_its_100mhz_6x86_clone_is_the_fastest |access-date=25 April 2022}}</ref> The 6x86 was made as a direct competitor to [[Intel|Intel's]] [[Pentium (original)|Pentium]] microprocessor line, and was pin compatible. 

During the 6x86's development, the majority of applications ([[office software]] as well as games) performed almost entirely [[integer]] operations. The designers foresaw that future applications would most likely maintain this instruction focus. So, to optimize the chip's performance for what they believed to be the most likely application of the CPU, the integer execution resources received most of the transistor budget. 

This would later prove to be a strategic mistake, as the popularity of the P5 Pentium caused many [[software developer]]s to hand-optimize code in [[X86 assembly language|assembly language]], to take advantage of the P5 Pentium's tightly [[instruction pipelining|pipelined]] and lower latency FPU. For example, the highly anticipated [[first-person shooter]] ''[[Quake (video game)|Quake]]'' used highly optimized assembly code designed almost entirely around the P5 Pentium's FPU. As a result, the P5 Pentium significantly outperformed other CPUs in the game.<ref>{{Cite web |last=Potoroaca |first=Adrian |date=30 December 2021 |title=Cyrix: Gone But Not Forgotten; Peak Cyrix Through the Lens of Quake |url=https://www.techspot.com/article/2120-cyrix/ |access-date=5 April 2022 |website=[[TechSpot]]}}</ref><ref>{{Cite web |last=Proven |first=Liam |date=5 June 2016 |title=The rise & fall of the first real x86 rival to Intel: the Cyrix 6x86 |url=https://liam-on-linux.livejournal.com/49259.html? |archive-url=https://web.archive.org/web/20210422004926/https://liam-on-linux.livejournal.com/49259.html |archive-date=22 April 2021 |access-date=5 April 2022 |website=Liam On Linux}}</ref><ref>{{Cite web |last=Shimpi |first=Anand |date=8 April 1997 |title=Cyrix 6x86 MX |url=https://www.anandtech.com/show/34 |archive-url=https://web.archive.org/web/20100418035705/http://www.anandtech.com/show/34 |url-status=dead |archive-date=April 18, 2010 |access-date=7 April 2022 |website=[[AnandTech]]}}</ref><ref>{{Cite news |last=Sood |first=Yatharth |date=24 July 2020 |title=How did a single game lead to the shake-up of an entire industry, and sounded the death knell of an entire corporation? |work=[[Medium (website)|Medium]] |url=https://yatharthsood.medium.com/how-did-a-single-game-lead-to-the-changing-of-a-whole-industry-and-the-death-knell-of-a-eeab5eb7f525 |access-date=7 April 2022}}</ref>

After Cyrix was bought by [[National Semiconductor]] then later [[VIA Technologies|VIA]], the 6x86 continued to be produced up until the early 2000s.

== History ==
The 6x86, previously under the codename "M1" was announced by Cyrix in October 1995.<ref name=":0" /><ref>{{Cite news |last=Metz |first=Cade |date=28 May 1996 |title=First Cyrix 6x86 PCs: How Good? How Fast? |volume=15 |pages=112 |work=[[PC Mag]] |publisher=[[Ziff Davis, Inc.]] |issue=10 |url=https://books.google.com/books?id=MPfwx4yZJTQC&dq=cyrix+6x86+announced&pg=PA112 |access-date=1 April 2022 |issn=0888-8507}}</ref><ref>{{Cite news |last=Vijayan |first=Jaikumar |date=16 October 1995 |title=Cyrix unveils Pentium-rival chips |volume=29 |work=[[Computerworld]] |publisher=[[IDG Enterprise]] |issue=42 |url=https://books.google.com/books?id=lp7gd8Y8RL4C&dq=cyrix+6x86&pg=PP49 |access-date=4 April 2022 |issn=0010-4841}}</ref><ref>{{Cite book |last=Minasi |first=Mark |url=https://books.google.com/books?id=ss5V_8ROo-cC |title=The Complete PC Upgrade and Maintenance Guide |publisher=[[Wiley (publisher)|Wiley]] |year=2004 |isbn=9780782143102 |publication-date=9 March 2004 |pages=56 |access-date=4 April 2022}}</ref><ref>{{Cite news |date=8 October 1995 |title=Cyrix introduces chip to challenge Pentium |pages=36 |work=[[News Record (Pennsylvania)|News Record]] |url=https://newscomwc.newspapers.com/image/41822320/?terms=Cyrix&pqsid=4nMGIIb3HCuVYj7bCUER2Q%3A95000%3A1923528434&match=1 |access-date=27 April 2022}}</ref> On release only the 100&nbsp;MHz (P120+) version was available, but a 120&nbsp;MHz (P150+) version was planned for mid-1995 with a 133&nbsp;MHz (P166+) model later. The 100&nbsp;MHz (P120+) 6x86 was available to [[OEM]]s for a price of $450 per chip in bulk quantities.<ref>{{Cite news |last=Metz |first=Cade |date=5 December 1995 |title=Cyrix's Sixth-Generation Chip; The 6x86 targets mainstream desktops |volume=14 |pages=29 |work=[[PC Mag]] |publisher=[[Ziff Davis, Inc.]] |issue=21 |url=https://books.google.com/books?id=FTbctntiaHgC&dq=cyrix+6x86+announced&pg=PA29 |access-date=1 April 2022 |issn=0888-8507}}</ref>

In mid February 1996 Cyrix announced the P166+, P150+, and P133+ to be added to the 6x86 model line.<ref name=":02">{{Cite news |last=Fisco |first=Richard |date=July 1996 |title=The Perfect Processor |volume=15 |pages=135–136 |work=[[PC Mag]] |publisher=[[Ziff Davis, Inc.]] |issue=13 |url=https://books.google.com/books?id=2KIKOEwqk-QC&dq=cyrix+6x86+announced&pg=PA136 |access-date=4 April 2022 |issn=0888-8507}}</ref> IBM, who produced the chips, also announced they will be selling their own versions of the chips.<ref>{{Cite news |last=Vijayan |first=Jaikumar |date=19 February 1996 |title=Closing in on performance; Intel competitors nip at Pentium's heels |volume=30 |pages=42 |work=[[Computerworld]] |publisher=[[IDG Enterprise]] |issue=8 |url=https://books.google.com/books?id=jwH_IrNuHmoC&dq=cyrix+6x86+announced&pg=PT41 |access-date=1 April 2022 |issn=0010-4841}}</ref>

The 6x86 P200+ was planned for the end of 1996,<ref name=":02" /> and ended up being released in June.<ref>{{Cite news |date=January 2003 |title=Chronology of the Processor |pages=45 |work=[[HWM (magazine)|HWM]] |publisher=[[SPH Magazines]] |url=https://books.google.com/books?id=SOoDAAAAMBAJ&dq=cyrix+6x86+P200%2B+announced&pg=PT46 |access-date=5 April 2022 |issn=0219-5607}}</ref>

The M2 (6x86MX) was first announced to be in development in mid 1996. It would have [[MMX (instruction set)|MMX]] and 32-bit optimization. The M2 would also have some of the same features as the Intel Pentium Pro such as register renaming, [[Out-of-order execution|out-of-order completion]], and speculative execution. Additionally it would have 64&nbsp;KB of cache over the original 6x86 and Pentium Pro's 16&nbsp;KB.<ref>{{Cite news |last=Metz |first=Cade |date=July 1996 |title=Cyrix's Bold M2 Strategy; Upcoming chip simplifies the upgrade decision |volume=15 |pages=36 |work=[[PC Mag]] |publisher=[[Ziff Davis, Inc.]] |issue=13 |url=https://books.google.com/books?id=2KIKOEwqk-QC&dq=cyrix+m2+announced&pg=PA36 |access-date=4 April 2022 |issn=0888-8507}}</ref> In March 1997 when asked about when the M2 line of processors would begin shipping, Cyrix UK managing director Brendan Sherry stated, "I've read it's going to be May but we've said late Q2 all along and I'm pretty sure we'll make that."<ref>{{Cite news |last=Veltech |first=Martin |date=26 March 1997 |title=M2 bang on time - Cyrix; Cyrix's M2 processor is getting ready to join the coming out party for a new generation of processors |work=[[ZDnet]] |url=https://www.zdnet.com/article/m2-bang-on-time-cyrix/ |access-date=5 April 2022 |archive-url=https://web.archive.org/web/20220405182523/https://www.zdnet.com/article/m2-bang-on-time-cyrix/ |archive-date=5 April 2022}}</ref>

The 6x86L was first released in January 1997 to address the heat issues with the original 6x86 line.<ref>{{Cite web |last=Hare |first=Chris |date=14 July 2008 |title=586/686 Processors Chart |url=https://www.pchardwarelinks.com/586.htm |access-date=27 April 2022 |website=PC Hardware Links}}</ref> The 6x86L had a lower V-core voltage and required a split power plane [[voltage regulator]].

In April 1997 the first laptop to use the 6x86 processor was put on sale. They were sold by [[TigerDirect]] and had a 12.1in [[DSTN]] display, 16&nbsp;MB of memory, 10x CD-ROM, 1.3&nbsp;GB hard disk drive, and cost $1,899 for the base price.<ref>{{Cite news |last=Crothers |first=Brooke |date=24 April 1997 |title=First Cyrix 6x86 notebook ships |work=[[Cnet]] |url=https://www.cnet.com/tech/tech-industry/first-cyrix-6x86-notebook-ships/ |access-date=3 May 2022}}</ref>

Later by the end of May 1997 on the 27th, Cyrix said they would announce details of the new chip line (6x86MX) the day before [[Computex]] in June 1997.<ref>{{Cite news |last=Veltech |first=Martin |date=27 May 1997 |title=Cyrix to announce M2 next week; Cyrix is expected to make the formal announcement of its M2 processor next week. |work=[[ZDnet]] |url=https://www.zdnet.com/article/cyrix-to-announce-m2-next-week/ |access-date=4 April 2022 |archive-url=https://web.archive.org/web/20220405183958/https://www.zdnet.com/article/cyrix-to-announce-m2-next-week/ |archive-date=5 April 2022}}</ref> For the low end of the series, the PR166 6x86MX was available for $190 with higher end PR200 and PR233 versions available for $240 and $320.<ref>{{Cite news |date=2 June 1997 |title=Cyrix Launches 6x86MX Processor |work=[[EETimes]] |url=https://www.eetimes.com/cyrix-launches-6x86mx-processor/ |access-date=5 April 2022}}</ref><ref>{{Cite news |last=Miller |first=Greg |date=30 May 1997 |title=Intel Facing Another Rival to Pentium II |work=[[The Los Angeles Times]] |url=https://www.latimes.com/archives/la-xpm-1997-05-30-fi-63884-story.html |access-date=25 April 2022}}</ref> IBM being the producer of Cyrix's chips, would also sell their own version. Cyrix hoped to ship tens of thousands within June 1997 with up to 1 million by the end of the year. Cyrix also expected to release a 266&nbsp;MHz chip by the end of 1997 and a 300&nbsp;MHz in the first quarter of 1998.<ref>{{Cite news |last=Crothers |first=Brooke |date=30 May 1997 |title=Cyrix introduces MMX chip; The 6x86MX will be a fast but cheap weapon in Cyrix's assault on the traditional processor pricing structure. |work=[[Cnet]] |url=https://www.cnet.com/tech/mobile/cyrix-introduces-mmx-chip/ |access-date=4 April 2022 |archive-url=https://web.archive.org/web/20220405185356/https://www.cnet.com/tech/mobile/cyrix-introduces-mmx-chip/ |archive-date=5 April 2022}}</ref> They had slightly better [[floating-point arithmetic|floating-point]] performance, which cut adding and multiply times by a third, but it was still slower than the Intel Pentium. The M2 also had full MMX instructions, 64&nbsp;KB of cache over the original 16&nbsp;KB, and had a lower core voltage of 2.5V over 3.3V of the original 6x86 line.<ref>{{Cite news |last=Crothers |first=Brooke |date=23 August 1996 |title=Intel and Cyrix duel for MMX |work=[[Cnet]] |url=https://www.cnet.com/tech/services-and-software/intel-and-cyrix-duel-for-mmx/ |access-date=25 April 2022}}</ref><ref>{{Cite book |last=Slater |first=Michael |url=https://www.ardent-tool.com/CPU/docs/MPR/19961028/101405.pdf |archive-url=https://web.archive.org/web/20211202222959/https://ardent-tool.com/CPU/docs/MPR/19961028/101405.pdf |archive-date=2021-12-02 |url-status=live |title=Cyrix Doubles 6x86 Performance with M2; MMX Added to Core; Larger Cache, Modified TLB Improve Scaling with Clock |publisher=Microprocessor Forum |year=1996 |volume=10 |publication-date=28 October 1996 |pages=1–3 |access-date=4 April 2022 |issue=14}}</ref>

National Semiconductor acquired Cyrix in July 1997.<ref name=":1">{{Cite news |last=Crothers |first=Brooke |date=2 January 2002 |title=National Semi leaving PC chip market |work=[[Cnet]] |url=https://www.cnet.com/tech/tech-industry/national-semi-leaving-pc-chip-market/ |access-date=11 April 2022}}</ref><ref>{{Cite news |date=30 July 1997 |title=National Semiconductor To Acquire Cyrix |work=[[Business Standard]] |url=https://www.business-standard.com/article/specials/national-semiconductor-to-acquire-cyrix-197073001117_1.html |access-date=11 April 2022}}</ref><ref>{{Cite news |last=Thurrott |first=Paul |date=27 July 1997 |title=National Semiconductor buys Cyrix |work=ITPro Today |url=https://www.itprotoday.com/windows-78/national-semiconductor-buys-cyrix |access-date=11 April 2022}}</ref> National Semiconductor was not interested in high performance processors but rather [[system on a chip]] devices, and wanted to shift the focus of Cyrix to the [[MediaGX]] line.<ref>{{Cite news |date=27 November 2020 |title=Intel's strongest competitor in history was not amd for a long time |work=[[China IT]] |url=https://www.firstxw.com/view/275405.html |access-date=11 April 2022}}</ref>

In January 1998 National Semiconductors produced a 6x86MX processor on a 0.25 [[micron]] process technology. This reduced the chip size from 150 square millimeters to 88.<ref>{{Cite news |date=12 January 1998 |title=National Produces First Functional Cyrix .25 Micron 6x86MX™ CPU |url=https://www.cpushack.com/CIC/announce/1998/Cy6x86MX-0.25.html |access-date=12 April 2022}}</ref> National shifted their production of the MII and MediaGX to 0.25 by August.<ref>{{Cite news |last=Kanellos |first=Michael |date=26 August 1998 |title=National starts making Cyrix chips; National Semiconductor has also begun producing the Cyrix-brand chips with the advanced 0.25-micron manufacturing process. |work=[[Cnet]] |url=https://www.cnet.com/tech/mobile/national-starts-making-cyrix-chips/ |access-date=6 May 2022}}</ref>

In September 1998 IBM's licensing partnership with Cyrix was said to be ended by National Semiconductors.<ref>{{Cite news |date=26 September 1998 |title=NATIONAL SEMICONDUCTOR HALTING I.B.M. AGREEMENT |work=[[The New York Times]] |url=https://www.nytimes.com/1998/09/26/business/company-news-national-semiconductor-halting-ibm-agreement.html |access-date=25 April 2022}}</ref><ref>{{Cite magazine |date=25 September 1998 |title=National Semi Dumps Big Blu |magazine=[[Wired (magazine)|Wired]] |url=https://www.wired.com/1998/09/national-semi-dumps-big-blue/ |access-date=25 April 2022}}</ref> This was due to National wanting to increase production of Cyrix chips in their own facilities, and because having IBM produce Cyrix's chips was causing issues such as profit losses due to IBM frequently pricing their versions of Cyrix's chips lower.<ref>{{Cite news |last=DiCarlo |first=Lisa |date=2 September 1998 |title=IBM to stop making Cyrix chips |work=[[ZDNet]] |url=https://www.zdnet.com/article/a-year-ago-ibm-to-stop-making-cyrix-chips/ |access-date=25 April 2022}}</ref> National would be paying $50–55 million to IBM to end the partnership, which would end the following April. National would then be moving chip production to their own facility in [[South Portland, Maine|South Portland]], [[Maine]].<ref>{{Cite news |last=Kalish |first=David |date=25 September 1998 |title=National Semi Ends IBM Chip Deal |work=[[CBS News]] |url=https://www.cbsnews.com/news/national-semi-ends-ibm-chip-deal/ |access-date=25 April 2022}}</ref><ref>{{Cite news |last=Tessler |first=Joelle |date=25 September 1998 |title=National Semi's Unit Breaks Off Manufacturing Deal With IBM |work=[[The Wall Street Journal]] |url=https://www.wsj.com/articles/SB906740793796057500 |access-date=25 April 2022}}</ref>

The Cyrix MII was released in May 1998. These chips were not exciting like people had hoped, as they were just a rebranding of the 6x86MX.<ref>{{Cite news |last=Shimpi |first=Anand |date=26 May 1998 |title=Cyrix M-II 300 |work=[[Anandtech]] |url=https://www.anandtech.com/show/170 |archive-url=https://web.archive.org/web/20110524184951/http://www.anandtech.com/show/170 |url-status=dead |archive-date=May 24, 2011 |access-date=4 April 2022}}</ref> In December these chips cost $80 for a MII-333, $59 for a MII-300, $55 for a MII-266, and $48 for a MII-233.<ref>{{Cite news |last=Magee |first=Mike |date=7 December 1998 |title=Cyrix takes axe to high-end MII prices; Battle to replace Intel after it dropped low end parts |work=[[The Register]] |url=https://www.theregister.com/1998/12/07/cyrix_takes_axe_to_highend/ |access-date=8 April 2022}}</ref>

In May 1999 National Semiconductor decided to leave the PC chip market due to significant losses, and put the Cyrix CPU division up for sale.<ref>{{Cite news |last=Fisher |first=Lawrence |date=10 May 1999 |title=National Semiconductor Quits the PC Chip Business |work=[[The New York Times]] |url=https://archive.nytimes.com/www.nytimes.com/library/tech/99/05/biztech/articles/10plac.html |access-date=11 April 2022}}</ref><ref name=":1" />

VIA bought the Cyrix line in June 1999, and ended the development of high performance processors. The MII-433GP would be the last processor produced by Cyrix.<ref>{{Cite news |last=Carroll |first=Mark |date=30 June 1999 |title=Via Technologies to acquire Cyrix |work=[[EETimes]] |url=https://www.eetimes.com/via-technologies-to-acquire-cyrix/ |access-date=8 April 2022}}</ref> Additionally after VIA's acquisition, the 6x86/L was discontinued, but the 6x86MX/MII line continued to be sold by VIA.<ref>{{Cite news |last=Mueller |first=Scott |year=2003 |title=Cyrix/IBM 6x86 (M1) and 6x86MX (MII) |pages=175–176 |work=[[Upgrading and Repairing PCs]] |publisher=[[Que Publishing|Que]] |isbn=9780789729743 |url=https://books.google.com/books?id=E1p2FDL7P5QC&dq=cyrix+6x86+discontinued&pg=PA176 |access-date=8 April 2022}}</ref><ref>{{Cite news | last=Hachman |first=Mark |date=17 November 1999 |title=Via Technologies' Samuel microprocess or to anchor 2000 chip lineup |work=[[EETimes]] |url=https://www.eetimes.com/via-technologies-samuel-microprocessor-to-anchor-2000-chip-lineup/ |access-date=26 April 2022}}</ref>

VIA would continue to produce the MII throughout the early 2000s. It was expected to be discontinued when the VIA Cyrix MII was released.<ref>{{Cite news | last=Hachman |first=Mark |date=17 November 1999 |title=Via Technologies' Samuel microprocessor to anchor 2000 chip lineup |work=[[EETimes]] |url=https://www.eetimes.com/via-technologies-samuel-microprocessor-to-anchor-2000-chip-lineup/ |access-date=26 April 2022}}</ref> However, the MII was still available for sale until mid/late 2003, being shown on VIA's website as a product until October, and it still saw use in devices such as network computers.<ref>{{Cite news |date=2 January 2002 |title=Ellison's Net computer gets a pricey accessory |work=[[CNet]] |url=https://www.cnet.com/culture/ellisons-net-computer-gets-a-pricey-accessory/#:~:text=Larry%20Ellison's%20New%20Internet%20Computer,%24199%20Internet%20appliance%20it%20complements.&text=Will%20consumers%20pay%20more%20than,as%20a%20cheap%20PC%20alternative%3F |access-date=26 April 2022}}</ref><ref>{{Cite web |date=25 June 2003 |title=VIA Cyrix® MII™ |url=http://www.viatech.com/en/viac3/cyrix_MII.jsp |access-date=26 April 2022 |archive-url=https://web.archive.org/web/20030625090820/http://www.viatech.com/en/viac3/cyrix_MII.jsp |archive-date=25 June 2003 |url-status=dead}}</ref>

==Architecture==
[[Image:Cyrix 6x86 arch.svg|250px|thumb|A simplistic block diagram of the Cyrix 6x86 [[microarchitecture]] ]]

The 6x86 is [[superscalar]] and [[superpipelined]] and performs [[register renaming]], [[speculative execution]], [[out-of-order execution]], and [[data dependency]] removal.<ref name="M1DataSheet">{{cite web |title=Cyrix M1 datasheet |url=http://datasheets.chipdb.org/Cyrix/M1/6x86/M1-1.PDF |publisher=Cyrix}}</ref> However, it continued to use native [[x86]] execution and ordinary [[microcode]] only, like [[Centaur Technology|Centaur]]'s [[Winchip]], unlike competitors [[Intel]] and [[AMD]] which introduced the method of dynamic translation to [[micro-operation]]s with [[Pentium Pro]] and [[AMD K5|K5]]. The 6x86 is [[CPU socket|socket]]-compatible with the Intel [[P5 (microarchitecture)#P54C|P54C]] [[Pentium (brand)|Pentium]], and was offered in six performance levels: PR 90+, PR 120+, PR 133+, PR 150+, PR 166+ and PR 200+. These performance levels do not map to the clock speed of the chip itself (for example, a PR 133+ ran at 110&nbsp;MHz, a PR 166+ ran at 133&nbsp;MHz, etc.).<ref>{{FOLDOC|Cyrix+6x86}}</ref>

With regard to internal caches, it has a 16-[[Kibibyte|KB]] primary [[CPU cache|cache]] and a fully associative 256-byte instruction line cache is included alongside the primary cache, which functions as the primary instruction cache.<ref name=M1DataSheet />

The 6x86 and 6x86L were not completely compatible with the Intel [[P5 (microarchitecture)|P5]] [[Pentium (brand)|Pentium]] [[instruction set]] and are not [[multi-processor]] capable. For this reason, the chip identified itself as an [[Intel 80486|80486]] and disabled the [[CPUID]] instruction by default. CPUID support could be enabled by first enabling extended [[condition code register|CCR]] registers then setting bit 7 in CCR4. The lack of full P5 Pentium compatibility caused problems with some applications because programmers had begun to use P5 Pentium-specific instructions. Some companies released patches for their products to make them function on the 6x86.

Compatibility with the Pentium was improved in the 6x86MX, by adding a [[Time Stamp Counter]] to support the P5 Pentium's RDTSC instruction.<ref name=6x86MXDataSheet>{{cite web |url=http://datasheets.chipdb.org/IBM/x86/6x86MX/mx_full.pdf |archive-url=https://web.archive.org/web/20140130164701/http://datasheets.chipdb.org/IBM/x86/6x86MX/mx_full.pdf |archive-date=2014-01-30 |url-status=live |title=IBM 6x86MX datasheet}}</ref> Support for the Pentium Pro's CMOVcc instructions were also added.<ref name=6x86MXDataSheet />

==Performance==
Similarly to [[Advanced Micro Devices|AMD]] with their [[AMD K5|K5]] and early [[AMD K6|K6]] processors, Cyrix used a [[PR rating]] (Performance Rating) to relate their performance to the Intel [[P5 (microarchitecture)|P5]] [[Pentium (brand)|Pentium]] (pre-[[P55C (microprocessor)|P55C]]), as the 6x86's higher per-clock performance relative to a P5 Pentium could be quantified against a higher-clocked Pentium part. For example, a 133&nbsp;MHz 6x86 will match or outperform a P5 Pentium at 166&nbsp;MHz, and as a result Cyrix could market the 133&nbsp;MHz chip as being a P5 Pentium 166's equal. However, the PR rating was not an entirely truthful representation of the 6x86's performance.<ref>{{Cite news |last=Phillips |first=Jon |date=July 2000 |title=The Pre-Fab Debate Continues |volume=5 |pages=16 |work=[[Maximum PC]] |publisher=[[Future US, Inc.]] |issue=7 |url=https://books.google.com/books?id=5QEAAAAAMBAJ&dq=cyrix+PR+rating&pg=PA16 |access-date=5 April 2022 |issn=1522-4279}}</ref>

While the 6x86's integer performance was significantly higher than P5 Pentium's, its floating-point performance was more mediocre—between 2 and 4 times the performance of the 486 FPU per clock cycle (depending on the operation and precision). The [[floating-point unit|FPU]] in the 6x86 was largely the same circuitry that was developed for Cyrix's earlier high performance [[8087]]/[[80287]]/[[80387]]-compatible coprocessors, which was very fast for its time—the Cyrix FPU was much faster than the 80387, and even the 80486 FPU. However, it was still considerably slower than the new and completely redesigned P5 Pentium and [[P6 (microarchitecture)|P6]] [[Pentium Pro]]-[[Pentium III]] FPUs. One of the main features of the P5/P6 FPUs is that they supported interleaving of FPU and integer instructions in their design, which Cyrix chips did not integrate. This caused very poor performance with Cyrix CPUs on games and software that took advantage of this.<ref>{{Cite web |last=Mury |first=John |title=CPU Considerations; Cyrix |url=https://www.oocities.org/timessquare/fortress/6191/cpu.html |access-date=7 April 2022 |website=NiNe's Rendition Quake Workshop}}</ref><ref>{{Cite web |last=Hsieh |first=Paul |date=7 September 1999 |title=6th Generation CPU Comparisons; The Cyrix 6x86MX |url=http://www.azillionmonkeys.com/qed/cpuwar.html |access-date=7 April 2022}}</ref>

Therefore, despite being very fast clock by clock, the 6x86 and MII were forced to compete at the low-end of the market as AMD K6 and Intel [[P6 (microarchitecture)|P6]] [[Pentium II]] were always ahead on clock speed. The 6x86's and MII's old generation "486 class" floating-point unit combined with an integer section that was at best on-par with the newer P6 and K6 chips meant that Cyrix could no longer compete in performance.

==Models and variants==

===6x86===
The ''6x86'' (codename M1) was released by [[Cyrix]] in 1996. The first generation of 6x86 had heat problems. This was primarily caused by their higher heat output than other x86 CPUs of the day and, as such, computer builders sometimes did not equip them with adequate cooling. The CPUs topped out at around 25&nbsp;[[Watt|W]] heat output (like the [[AMD K6]]), whereas the P5 Pentium produced around 15&nbsp;W of [[waste heat]] at its peak. However, both numbers would be a fraction of the heat generated by many high performance processors, some years later. Shortly after the original M1, the M1R was released. The M1R was a switch from SGS-Thomson 3M process to IBM 5M process, making the 6x86 chips 50% smaller.<gallery mode="packed" heights="200px">
Image:Cyrix_6x86_early_die.jpg|Early Cyrix 6x86 (M1) die shot
</gallery>

===6x86L===
The '''6x86L''' (codename M1L) was later released by [[Cyrix]] to address heat issues; the ''L'' standing for ''low-power''. Improved manufacturing technologies permitted usage of a lower Vcore. Just like the [[Pentium MMX]], the 6x86L required a split power plane voltage regulator with separate voltages for I/O and CPU core.

<gallery mode="packed" heights="200px">
Image:Cyrix_6x86_die.JPG|Cyrix 6x86L (M1L) die shot
</gallery>

===6x86MX / MII===
Another release of the 6x86, the '''6x86MX''', added [[MMX (instruction set)|MMX]] compatibility along with the [[Extended MMX|EMMI]] instruction set, improved compatibility with the Pentium and Pentium Pro by adding a [[Time Stamp Counter]] and CMOVcc instructions respectively, and quadrupled the primary cache size to 64&nbsp;KB. The 256-byte instruction line cache can be turned into a [[Scratchpad memory|scratchpad cache]] to provide support for multimedia operations.<ref name=6x86MXDataSheet /> Later revisions of this chip were renamed '''MII''', to better compete with the Pentium II processor. 6x86MX / '''MII''' was late to market, and couldn't scale well in clock speed with the manufacturing processes used at the time.

<gallery mode="nolines" heights="200" widths="200" perrow="1" style="margin-left: auto; margin-right: auto;">
File:Cyrix 6x86MX die.JPG|Cyrix 6x86MX (M2) die shot
</gallery>

=== Model table ===
{| class="wikitable mw-collapsible mw-collapsed"
!Images
!Model
!Core name
!Process size<br />([[Micrometre|μm]])
!Die area<br />([[Square millimeter|mm<sup>2</sup>]])
!Number of transistors<br />(millions)
!Socket(s)
!Package
!Core Voltage
!TDP (W)
!Clock speed
!Bus Speed
!L1 Cache
!Price (USD)
!Launch
|-
| rowspan="6" |<gallery mode="nolines" widths="80" heights="80" perrow="1" style="margin-left: auto; margin-right: auto;">
File:KL Cyrix 6x86.jpg
File:Cyrix 6x86-P166.jpg
</gallery>
|PR90+
|M1
|0,65
|394
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.3
|15.5
|80&nbsp;MHz
|40&nbsp;MHz
|16 KB
|$84
|Nov 1995
|-
|PR120+
|M1
|0,65
|394
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.3
|?
|100&nbsp;MHz
|50&nbsp;MHz
|16 KB
|$450
|Oct 1995
|-
|PR133+
|M1R
|0,65
|225
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.3
|19.1
|110&nbsp;MHz
|55&nbsp;MHz
|16 KB
|$326
|2-5-1996
|-
|PR150+
|M1R
|0,65
|225
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.3/3.52
|20.1
|120&nbsp;MHz
|60&nbsp;MHz
|16 KB
|$451
|2-5-1996
|-
|PR166+
|M1R
|0,65
|225
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.3/3.52
|21.8
|133&nbsp;MHz
|66&nbsp;MHz
|16 KB
|$621
|2-5-1996
|-
|PR200+
|M1R
|0,44
|?
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.52
|17.13
|150&nbsp;MHz
|75&nbsp;MHz
|16 KB
|$499
|6-6-1996
|-
| rowspan="5" |<gallery mode="nolines" widths="80" heights="80" perrow="1" style="margin-left: auto; margin-right: auto;">
File:Cyrix6x86L-PR166.jpg
File:KL Cyrix 6x86L.jpg
</gallery>
|L-PR120+
|M1L
|0,35
|169
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.8/3.3
|?
|100&nbsp;MHz
|50&nbsp;MHz
|16 KB
|?
|Jan-1997
|-
|L-PR133+
|M1L
|0,35
|169
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.8/3.3
|?
|110&nbsp;MHz
|55&nbsp;MHz
|16 KB
|?
|Feb-1997
|-
|L-PR150+
|M1L
|0,35
|169
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.8/3.3
|?
|120&nbsp;MHz
|60&nbsp;MHz
|16 KB
|?
|Mar-1997
|-
|L-PR166+
|M1L
|0,35
|169
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.8/3.3
|15.98
|133&nbsp;MHz
|66&nbsp;MHz
|16 KB
|?
|Apr-1997
|-
|L-PR200+
|M1L
|0,35
|169
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.8/3.3
|17.13
|150&nbsp;MHz
|75&nbsp;MHz
|16 KB
|?
|Apr-1997
|-
| rowspan="4" |<gallery mode="nolines" widths="80" heights="80" perrow="1" style="margin-left: auto; margin-right: auto;">
File:KL Cyrix 6x86MX.jpg
File:Ic-photo-Cyrix--6x86MX-PR233--(6x86MX-CPU).png
</gallery>
|PR166-MMX
|MII
|0,35
|197
|6.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
?
|133&nbsp;MHz
150&nbsp;MHz
|66&nbsp;MHz
60&nbsp;MHz
|64 KB
|$190
?
|5-30-97
Q2 1998
|-
|PR200-MMX
|MII
|0,35 ([[IBM]])
0,30 ([[National Semiconductor|NS]])
|197
156
|6.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
?
|150&nbsp;MHz
166&nbsp;MHz
|75&nbsp;MHz
66&nbsp;MHz
|64 KB
|$240
?
|5-30-97
Q2 1998
|-
|PR233-MMX
|MII
|0,35 ([[IBM]])
0,30 ([[National Semiconductor|NS]])
|197
156
|6.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
?
|188&nbsp;MHz
200&nbsp;MHz
|75&nbsp;MHz
66&nbsp;MHz
|64 KB
|$320
?
|5-30-97
Q2 1998
|-
|PR266-MMX
|MII
|0,35 ([[IBM]])
0,30 ([[National Semiconductor|NS]])
|197
156
|6.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
|208&nbsp;MHz
|83&nbsp;MHz
|64 KB
|$180
?
|3-19-98
Q2 1998
|-
| rowspan="6" |<gallery mode="nolines" widths="80" heights="80" perrow="1" style="margin-left: auto; margin-right: auto;">
File:Cyrix-m2-233gp 75x2.5.jpg
File:KL Cyrix MII-333.jpg
File:Cyrix M II-433GP - 300MHz CPU 1998 front.jpg
</gallery>
|MII-300-MMX (*m)
|MII
|0,30
0,25
|156
88
|6.0
|[[Super Socket 7|Super 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
2.2 (*m)
|?
?
|233&nbsp;MHz
225&nbsp;MHz
|66&nbsp;MHz
75&nbsp;MHz
|64 KB
|$180
?
|4-14-98
Q1 1999
|-
|MII-333-MMX (*m)
|MII
|0,30
0,25
|156
88
|6.0
|[[Super Socket 7|Super 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
2.2 (*m)
|?
?
|250&nbsp;MHz
|100&nbsp;MHz
83&nbsp;MHz
|64 KB
|$180
?
|6-15-98
Mar-1999
|-
|MII-350-MMX
|MII
|0,25
|88
|6.0
|[[Super Socket 7|Super 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
|270&nbsp;MHz
250&nbsp;MHz
|90&nbsp;MHz
83&nbsp;MHz
|64 KB
|?
?
|?
?
|-
|MII-366-MMX 
|MII
|0,25
|88
|6.0
|[[Super Socket 7|Super 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
|250&nbsp;MHz
|100&nbsp;MHz
|64 KB
|?
|Mar-1999
|-
|MII-400-MMX (*m)
|MII
|0,18
|65
|6.0
|[[Super Socket 7|Super 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.2/3.3
|?
|285&nbsp;MHz
|95&nbsp;MHz
|64 KB
|?
|Jun-1999
|-
|MII-433-MMX (*m)
|MII
|0,18
|65
|6.0
|[[Super Socket 7|Super 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.2/3.3
|?
|300&nbsp;MHz
|100&nbsp;MHz
|64 KB
|?
|Jun-1999
|-
| rowspan="7" |<gallery mode="nolines" widths="80" heights="80" perrow="1" style="margin-left: auto; margin-right: auto;">
File:Cyrix 6x86 P150+ CPU.jpg
</gallery>
! colspan="14" |SGS-Thomson 6x86 Models
|-
|ST6x86P90+HS
|M1
|0,65
|394
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.52
|17.39
|80&nbsp;MHz
|40&nbsp;MHz
|16 KB
|?
|?
|-
|ST6x86P120+HS
|M1
|0,65
|394
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.52
|19.98
|100&nbsp;MHz
|50&nbsp;MHz
|16 KB
|?
|2-5-1996
|-
|ST6x86P133+HS
|M1
|0,65
|394
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.52
|21.46
|110&nbsp;MHz
|55&nbsp;MHz
|16 KB
|?
|2-5-1996
|-
|ST6x86P150+HS
|M1
|0,65
|225
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.52
|?
|120&nbsp;MHz
|60&nbsp;MHz
|16 KB
|?
|2-5-1996
|-
|ST6x86P166+HS
|M1
|0,65
|225
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.52
|?
|133&nbsp;MHz
|66&nbsp;MHz
|16 KB
|?
|2-5-1996
|-
|ST6x86P200+HS
|M1
|0,44
|?
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.52
|?
|150&nbsp;MHz
|75&nbsp;MHz
|16 KB
|?
|?
|-
| rowspan="7" |<gallery mode="nolines" widths="80" heights="80" perrow="1" style="margin-left: auto; margin-right: auto;">
File:IBM 6x86 P150+ CPU.jpg
File:KL IBM 6x86 P166+ Cyrix.jpg
</gallery>
! colspan="14" |IBM 6x86 Models
|-
|<sub>2V2100&nbsp;GB</sub>
|M1
|0,65
|394
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.3
|?
|80&nbsp;MHz
|40&nbsp;MHz
|16 KB
|?
|?
|-
|<sub>2V2P120GC</sub>
|M1
|0,65
|394
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.3
|?
|100&nbsp;MHz
|50&nbsp;MHz
|16 KB
|?
|?
|-
|<sub>2V2120&nbsp;GB</sub>
|M1R
|0,65
|394
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.33
|?
|100&nbsp;MHz
|50&nbsp;MHz
|16 KB
|?
|?
|-
|<sub>2V2P150GE</sub>
|M1R
|0,65
|225
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.3/3.52
|?
|120&nbsp;MHz
|60&nbsp;MHz
|16 KB
|?
|2-5-1996
|-
|<sub>2V2P166GE</sub>
|M1R
|0,65
|225
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.3/3.52
|21.8
|133&nbsp;MHz
|66&nbsp;MHz
|16 KB
|?
|2-5-1996
|-
|<sub>2V7P200GE</sub>
|M1R
|0,44
|?
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|3.52
|14
|150&nbsp;MHz
|75&nbsp;MHz
|16 KB
|?
|2-5-1996
|-
| rowspan="4" |<gallery mode="nolines" widths="80" heights="80" perrow="1" style="margin-left: auto; margin-right: auto;">
File:KL IBM 6x86L Cyrix.jpg
</gallery>
|<sub>2VAP120&nbsp;GB</sub>
|M1L
|0,35
|169
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.8
|?
|100&nbsp;MHz
|50&nbsp;MHz
|16 KB
|?
|?
|-
|<sub>2VAP150&nbsp;GB</sub>
|M1L
|0,35
|169
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.8
|?
|120&nbsp;MHz
|60&nbsp;MHz
|16 KB
|?
|?
|-
|<sub>2VAP166&nbsp;GB</sub>
|M1L
|0,35
|169
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.8
|?
|133&nbsp;MHz
|66&nbsp;MHz
|16 KB
|?
|?
|-
|<sub>2VAP200&nbsp;GB</sub>
|M1L
|0,35
|169
|3.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.8
|?
|150&nbsp;MHz
|75&nbsp;MHz
|16 KB
|?
|?
|-
| rowspan="12" |<gallery mode="nolines" widths="80" heights="80" perrow="1" style="margin-left: auto; margin-right: auto;">
File:KL IBM 6x86MX.jpg
File:Cyrix IBM CPU 6x86MX PR200 top.jpg
File:IBM PR300.jpg
</gallery>
|<sub>AVAPR166&nbsp;GB</sub>
|MII
|0,35
|197
|6.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
|133&nbsp;MHz
|66&nbsp;MHz
|64 KB
|$202
|5-30-97
|-
|?
|MII
|0,35
|197
|6.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
|150&nbsp;MHz
|60&nbsp;MHz
|64 KB
|?
|5-30-97
|-
|<sub>BVAPR200&nbsp;GB</sub>
|MII
|0,35
|?
|6.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
|150&nbsp;MHz
|75&nbsp;MHz
|64 KB
|$369
|5-30-97
|-
|<sub>AVAPR200GA</sub>
|MII
|0,30
|?
|6.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
|166&nbsp;MHz
|66 MHz
|64 KB
|?
|Q2 1998
|-
|<sub>BVAPR233GC</sub>
|MII
|0,35
|?
|6.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
|166&nbsp;MHz
|83&nbsp;MHz
|64 KB
|$477
|5-30-97
|-
|<sub>AVAPR233&nbsp;GB</sub>
|MII
|0,30
|?
|6.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
|188&nbsp;MHz
|75&nbsp;MHz
|64 KB
|?
|Q2 1998
|-
|<sub>BVAPR233GD</sub>
|MII
|0,30
|?
|6.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
|200&nbsp;MHz
|66&nbsp;MHz
|64 KB
|?
|Q2 1998
|-
|<sub>BVAPR266GE</sub>
|MII
|0,35
0,30
|?
|6.0
|[[Socket 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
|208&nbsp;MHz
|83&nbsp;MHz
|64 KB
|?
|3-19-98
Q2 1998
|-
|<sub>CVAPR300GF (*m)</sub>
|MII
|0,25
|119
|6.0
|[[Super Socket 7|Super 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
|225&nbsp;MHz
|75&nbsp;MHz
|64 KB
|$217
|3-19-98
|-
|<sub>DVAPR300GF (*m)</sub>
|MII
|0,25
|119
|6.0
|[[Super Socket 7|Super 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
|233&nbsp;MHz
|66&nbsp;MHz
|64 KB
|?
|?
|-
|<sub>CVAPR333GF (*m)</sub>
|MII
|0,25
|119
|6.0
|[[Super Socket 7|Super 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
2.2 (*m)
|?

|250&nbsp;MHz
|83&nbsp;MHz
|64 KB
|$299
|3-19-98
|-
|?
|MII
|0,25
|119
|6.0
|[[Super Socket 7|Super 7]]
|[[Ceramic Pin Grid Array|CPGA]]
|2.9/3.3
|?
|263&nbsp;MHz
|75&nbsp;MHz
|64 KB
|?
|?
|-
| colspan="15" |? - Missing information
<nowiki>*</nowiki>m -Available in mobile version for laptops

Information From:

* https://www.pchardwarelinks.com/586.htm
* https://www.cpu-world.com/CPUs/6x86/
* https://www.x86-guide.net/
* http://www.cpu-galerie.de/
|}

==Timeline==
{{Timeline of Cyrix products}}

==See also==
===Competitors===
* [[Pentium (original)|Pentium, Original]]
* [[Pentium II]]
* [[AMD K5]]
* [[AMD K6]]
* rise [[mP6]]
* [[WinChip]]

==References==
{{Reflist}}

==Further reading==
*Gwennap, Linley (October 25, 1993). "Cyrix Describes Pentium Competitor" ''[[Microprocessor Report]]''.
*Gwennap, Linley (December 5, 1994). "Cyrix M1 Design Tapes Out". ''[[Microprocessor Report]]''.
*Gwennap, Linley (June 2, 1997). "Cyrix 6x68MX Outperforms AMD K6". ''[[Microprocessor Report]]''.
*Slater, Michael (February 12, 1996). "[https://www.ardent-tool.com/CPU/docs/MPR/19960212/100202.pdf Cyrix, IBM Push 6x86 to 133&nbsp;MHz]". ''[[Microprocessor Report]]''.
*Slater, Michael (October 28, 1996). "Cyrix Doubles x86 Performance with M2". ''[[Microprocessor Report]]''.

==External links==
* {{webarchive |url=https://web.archive.org/web/20170622042421/http://www.pcguide.com/ref/cpu/fam/g5C6x86-c.html |date=June 22, 2017 |title=Cyrix 6x86 ("M1") at The PC Guide }}
*[http://www.cpu-collection.de/?l0=co&l1=Cyrix&l2=6x86 cpu-collection.de] Cyrix 6x86 processor images and descriptions
*[http://www.azillionmonkeys.com/qed/cpuwar.html#6x86MX Paul Hsieh's 6th Generation x86 CPU Comparison] in-depth analysis of 6th generation x86 CPUs, including the 6x86MX.
*[https://web.archive.org/web/20060615180354/http://www.sandpile.org/impl/m1.htm Cyrix M1 stats] at Sandpile.org

===Cyrix Datasheets===
* [http://datasheets.chipdb.org/Cyrix/M1/6x86/M1-1.PDF 6x86 (M1/M1R) Guide]
* [http://datasheets.chipdb.org/Cyrix/M1/6x86/6xtbengl.pdf 6x86 (M1/M1R) Technical Brief]
* [https://www.ardent-tool.com/CPU/docs/Cyrix/6x86MX/94329.pdf 6x86 (MX) Guide]
* [https://www.ardent-tool.com/CPU/docs/Cyrix/6x86MX/94345.pdf 6x86 (MX) Technical Brief]
* [https://www.ardent-tool.com/CPU/docs/Cyrix/MII/94405.pdf 6x86 (MII) Technical Brief]

{{Cyrix}}

[[Category:Cyrix x86 microprocessors|686]]
[[Category:Computer-related introductions in 1995]]
[[Category:Superscalar microprocessors]]
[[Category:X86 microarchitectures]]