View source for Compact Model Coalition

The '''Compact Model Coalition'''<ref>{{Cite web |title=Compact Model Coalition |url=https://si2.org/compact-model-coalition/ |access-date=2025-05-09 |website=Si2 |language=en}}</ref> (formerly the '''Compact Model Council''')<ref>{{cite web|url=http://www.geia.org/index.asp?bid=597 |title=CMC - Compact Model Council |publisher=Government Electronics & Information Technology Association (GEIA) |url-status=dead |archiveurl=https://web.archive.org/web/20110511071827/http://www.geia.org/index.asp?bid=597 |archivedate=2011-05-11 }}</ref> is a working group in the [[electronic design automation|electronic design automation (EDA)]] industry formed to choose, maintain and promote the use of standard [[Semiconductor device modeling|semiconductor device models]].<ref>{{cite web|url=http://www.geia.org/index.asp?bid=1333 |title=Standard Models and Downloads |publisher=Government Electronics & Information Technology Association (GEIA) |url-status=dead |archiveurl=https://web.archive.org/web/20110720190121/http://www.geia.org/index.asp?bid=1333 |archivedate=2011-07-20 }}</ref>  Commercial and industrial analog simulators (such as [[SPICE]]) need to add device models as technology advances (see [[Moore's law]]) and earlier models become inaccurate.   Before this group was formed, new [[transistor models]] were largely proprietary, which severely limited the choice of simulators that could be used.

It was formed in August, 1996, for the purpose developing and standardizing the use and implementation of SPICE models and the model interfaces. In May 2013, the [[Silicon Integration Initiative]] (Si2) and [[TechAmerica]] announced the transfer of the Compact Model Council to Si2 and a renaming to Compact Model Coalition.<ref name="si2">{{Cite web
| title = CMC Moves to Si2
| author = 
| work = Silicon Integration Initiative, Inc
| date = 
| accessdate = 2015-10-19
| url = http://www.si2.org/?page=1650
| language =  
| quote = 
}}</ref>

To develop and maintain the models, the CMC works with device modeling and simulation experts belonging to an international collection of universities and research institutions.   In alphabetical order, the present development organizations are [[Auburn University]] (SiGe group),<ref>{{Cite web |title=SiGe Research — Dr. Guofu Niu |url=https://www.eng.auburn.edu/~niuguof/research/index.html |access-date=2025-05-09 |website=www.eng.auburn.edu}}</ref> [[CEA-Leti: Laboratoire d'électronique des technologies de l'information|CEA-LETI]], [[Hiroshima University]] (HiSIM Research Center),<ref>{{Cite web |title=toppage {{!}} HiSIM Research Center |url=https://www.hisim.hiroshima-u.ac.jp/index.php?id=87 |access-date=2025-05-09 |website=www.hisim.hiroshima-u.ac.jp}}</ref> [[Macquarie University]], [[TU Dresden]] (HiCUM development),<ref>{{Cite web |title=HICUM |url=https://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_intro.html}}</ref> [[University of California, Berkeley|UC Berkeley]] (BSIM Group),<ref>{{Cite web |title=BSIM Group UC Berkeley |url=https://bsim.berkeley.edu |access-date=2025-05-09 |language=en-US}}</ref> and [[University of Waterloo]] (WEIS Group).<ref>{{Cite web |title=MVSG model {{!}} Waterloo Emerging Integrated Systems Group (WEIS) {{!}} University of Waterloo |url=https://uwaterloo.ca/waterloo-emerging-integrated-systems-group/mvsg-model |access-date=2025-05-09 |website=uwaterloo.ca |language=en}}</ref>   Though the development is done at these different institutions, all of them follow the same Verilog-A coding standards<ref name=":0">{{Cite web |last=Berke |first=Terry |date=2025-03-16 |title=CMC Releases Coding Standard Guidelines for Verilog-A Model Code |url=https://si2.org/cmc-releases-coding-standard-guidelines-for-verilog-a-model-code/ |access-date=2025-05-09 |website=Si2 |language=en}}</ref> and QA standards, and they all go through a common beta testing and release process.<ref>{{Cite web |last=Justin |first=Xie |date=March 14, 2018 |title=How is a CMC Standard Model Implemented and Verified in a Simulator |url=https://www.mos-ak.org/munich_2018/presentations/T_6_Xie_MOS-AK_Munich_2018.pdf}}</ref>  CMC maintains a workgroup for each standardized model, composed of interested industry members and the model developers.

Most of the CMC development is industry-funded, supported by dues from CMC member companies.  The member companies primarily are silicon design companies, silicon foundry companies, [[Integrated Device Manufacturer]]s (IDM), and silicon design [[Electronic design automation|EDA]] companies.

Production releases of industry-funded CMC models are available to the public free of charge.  The CMC member companies have access to earlier pre-production versions of those models, and they have the opportunity to help direct the evolution of those models.

The industry-funded CMC models, listed alphabetically,  are:

{| class="wikitable"
|+
!Model Name
!Developer
!Description
|-
|ASM-ESD<ref>{{Cite book |last1=Khandelwal |first1=S. |last2=Bavi |first2=D. |chapter=ASM-ESD – A comprehensive physics-based compact model for ESD Diodes |date=2022 |title=2022 IEEE International Reliability Physics Symposium (IRPS) |chapter-url=https://researchers.mq.edu.au/en/publications/asm-esd-a-comprehensive-physics-based-compact-model-for-esd-diode |pages=5C.1–1–5C.1–6 |doi=10.1109/IRPS48227.2022.9764453|isbn=978-1-6654-7950-9 }}</ref>
|Macquarie University
|Advanced SPICE models for ESD diodes
|-
|ASM-HEMT<ref>{{Cite web |title=ASM-HEMT Compact Model for GaN RF and Power Devices |url=https://researchers.mq.edu.au/en/impacts/asm-hemt-compact-model-for-gan-rf-and-power-devices |access-date=2025-05-09 |website=Macquarie University |language=en}}</ref>
|Macquarie University
|Advanced SPICE models for High Electron Mobility GaN [[High-electron-mobility transistor|HEMT]] Transistors.  The physical model is surface potential based and is computationally efficient by virtue of being completely analytical. It includes velocity saturation effects, access region resistance effects, DIBL, temperature dependence and models for gate current and noise.
|-
|BSIM-Bulk (and BSIM4)<ref>{{Cite web |date=2016-03-13 |title=BSIM-BULK {{!}} BSIM GROUP |url=https://www.bsim.berkeley.edu/models/bsimbulk/ |access-date=2025-05-09 |language=en-US}}</ref><ref>{{Cite web |date=2016-03-13 |title=BSIM4 {{!}} BSIM GROUP |url=https://www.bsim.berkeley.edu/models/bsim4/ |access-date=2025-05-09 |language=en-US}}</ref>
|UC Berkeley
|BSIM (Berkeley Short Channel IGFET Mode)-BULK is a new surface potential based Bulk [[MOSFET]] model.  It features model symmetry valued for analog and RF applications while maintaining the strong support and performance of the BSIM model valued for all applications since 1996.
|-
|BSIM-CMG<ref>{{Cite web |date=2024-09-09 |title=BSIM-CMG {{!}} BSIM GROUP |url=https://www.bsim.berkeley.edu/models/bsimcmg/ |access-date=2025-05-09 |language=en-US}}</ref>
|UC Berkeley
|BSIM-CMG (Common Multi-Gate) models 3D multi-gate devices where the multiple gate surfaces act electrically as a single gate
|-
|BSIM-IMG<ref>{{Cite web |date=2016-03-13 |title=BSIM-IMG {{!}} BSIM GROUP |url=https://www.bsim.berkeley.edu/models/bsimimg/ |access-date=2025-05-09 |language=en-US}}</ref>
|UC Berkeley
|BSIM-IMG (Independent Multi-Gate) models the electrical characteristics of the independent double-gate structures like Ultra-Thin Body and BOX SOI ([[Silicon on insulator|Silicon on Insulator]]) transistors (UTBB).
|-
|BSIM-SOI<ref>{{Cite web |date=2024-09-09 |title=BSIM-SOI {{!}} BSIM GROUP |url=https://www.bsim.berkeley.edu/models/bsimsoi/ |access-date=2025-05-09 |language=en-US}}</ref>
|UC Berkeley
|Standard model for planar SOI ([[Silicon on Insulator]]) devices.  The foundation of this model is the BSIM3<ref>{{Cite web |date=2016-03-21 |title=BSIM3 {{!}} BSIM GROUP |url=https://www.bsim.berkeley.edu/models/bsim3/ |access-date=2025-05-09 |language=en-US}}</ref> framework.  A newer version based on surface potential concepts is also being released which ensures complete model symmetry.
|-
|HICUM_L0<ref name=":1">{{Cite web |date=February 21, 2020 |title=HICUM Introduction |url=https://www.iee.et.tu-dresden.de/iee/eb/hic_new/hic_intro.html}}</ref>
|ADM Enterprises (TU Dresden)
|High CUrrent Model for [[Bipolar junction transistor|bipolar]] transistors.  It addresses modern BJT and HBT technologies by including more accurate modeling than the [[Gummel–Poon model|Gummel-Poon model]] for important physical effects such as forward transit time, base-collector punch-through and collector impact ionization. Compared to HiCUM_L2, HiCUM_L0 targets faster simulation speed, so it gives up some accuracy at high frequencies and high current densities.
|-
|HICUM_L2<ref name=":1" />
|ADM Enterprises (TU Dresden)
|HICUM stands for HIgh CUrrent Model and targets the design of bipolar transistor circuits at high-frequencies and high-current densities using a wide range of Si, SiGe or III-V based process technologies. HICUM_L2 is an advanced physics-based compact model that contains accurate formulations of all known physical effects, enables geometry scaling and statistical modeling, and covers a wide temperature, operating and frequency range.
|-
|HiSIM2<ref>{{Cite web |last=Mattausch |first=H.J |date=October 2006 |title=HISIM2 Circuit Simulation - Solving the Speed vs. Accuracy Crisis |url=https://www.researchgate.net/publication/3345830}}</ref>
|Hiroshima University
|HiSIM (Hiroshima University STARC IGFET Model) is a surface-potential based [[MOSFET]] model based on the drift diffusion approximation.
|-
|HiSIM_HV<ref>{{Cite web |title= |url=https://www.researchgate.net/publication/283103879 |archive-url=http://web.archive.org/web/20210114204207/https://www.researchgate.net/profile/Hj-Mattausch/publication/283103879_The_HiSIM_compact_models_of_high-voltagepower_semiconductor_devices_for_circuit_simulation/links/5673e81508aedbbb3fa1a08f/The-HiSIM-compact-models-of-high-voltage-power-semiconductor-devices-for-circuit-simulation.pdf |archive-date=2021-01-14 |access-date=2025-05-09 |website=www.researchgate.net}}</ref>
|Hiroshima University
|HiSIM-HV is for accurate modeling of high-voltage [[MOSFET]]s
|-
|HiSIM_SOI<ref>{{Cite book |last1=Miyake |first1=M. |last2=Kusu |first2=S. |last3=Kikuchihara |first3=H. |last4=Tanaka |first4=A. |last5=Shintaku |first5=Y. |last6=Ueno |first6=M. |last7=Nakashima |first7=J. |last8=Feldmann |first8=U. |last9=Mattausch |first9=H. J. |last10=Miura-Mattausch |first10=M. |last11=Yoshida |first11=T. |chapter=The flexible compact SOI-MOSFET model HiSIM-SOI valid for any structural types |date=September 2011 |title=2011 International Conference on Simulation of Semiconductor Processes and Devices |chapter-url=https://ieeexplore.ieee.org/document/6034968 |pages=167–170 |doi=10.1109/SISPAD.2011.6034968|isbn=978-1-61284-419-0 }}</ref>
|Hiroshima University
|HiSIM_SOI is a surface-potential-based SOI [[MOSFET]] model for circuit simulation based on the drift-diffusion approximation
|-
|HiSIM_SOTB<ref>{{Cite web |title=[Research]HiSIM-SOTB, compact transistor model, selected as international industry standard {{!}} Hiroshima University |url=https://www.hiroshima-u.ac.jp/en/news/5055 |access-date=2025-05-09 |website=www.hiroshima-u.ac.jp |language=ja}}</ref>
|Hiroshima University
|HiSIM_SOTB accurately models the ultra-thin-body SOI MOSFET, a practical transistor structure for super-low power consumption.
|-
|L_UTSOI<ref>{{Cite web |last=CEA |date=2020-04-02 |title=Compact Model Developed at CEA-Leti for FD-SOI Technologies Designated as a Chip-Industry Standard |url=https://www.leti-cea.com/cea-tech/leti/english/Pages/What's-On/Press%20release/Compact-Model-Developed-at-CEA-Leti-for-FD-SOI-Technologies-Designated-as-a-Chip-Industry-Standard.aspx |access-date=2025-05-09 |website=CEA/Leti (english) |language=en}}</ref>
|CEA-LETI
|L-UTSOI ("L" for LETI, from CEA-LETI) is dedicated to ultra-thin-body Fully Depleted SOI (FDSOI) technologies.  The L-UTSOI model is able to physically describe FDSOI transistor behavior for any bias configuration, including the case of strong forward back bias where two channels exist at the front and back interfaces of a thin silicon body.
|-
|MEXTRAM<ref>{{Cite web |title=CMC Mextram Development — Dr. Guofu Niu |url=https://www.eng.auburn.edu/~niuguof/research/mextram.html |access-date=2025-05-09 |website=www.eng.auburn.edu}}</ref>
|Auburn University
|MEXTRAM is an advanced compact model for the description of bipolar transistors.   It contains many features that the widely-used [[Gummel–Poon model|Gummel-Poon model]] lacks. Mextram can be used for advanced processes like double-poly or even SiGe transistors, for high-voltage power devices, and even for uncommon situations like lateral NPN-transistors in LDMOS technology.
|-
|MVSG<ref>{{Cite web |title=MVSG model {{!}} Waterloo Emerging Integrated Systems Group (WEIS) |url=https://uwaterloo.ca/waterloo-emerging-integrated-systems-group/mvsg-model |archive-url=http://web.archive.org/web/20240706060342/https://uwaterloo.ca/waterloo-emerging-integrated-systems-group/mvsg-model |archive-date=2024-07-06 |access-date=2025-05-09 |website=uwaterloo.ca |language=en-CA}}</ref>
|MIT, U. of Waterloo
|The MVSG model is a physical model for [[Gallium nitride|GaN]] HEMTs that includes formulations for currents and charges that can be used for GaN-based circuit simulations, in particular RF- and HV-applications.
|-
|PSP<ref>{{Cite web |date=October 19, 2013 |title=PSP Support, CEA-LETI |url=https://www.cea.fr/cea-tech/leti/pspsupport}}</ref>
|CEA-LETI
|PSP is a surface-potential-based MOS model containing all relevant physical effects (mobility reduction, velocity saturation, DIBL, gate current, lateral doping effects, STI stress, etc.) to model present-day and upcoming deep-submicron bulk CMOS technologies.   Development of this model started with NXP and University of Arizona, then University of Delft, and now CEA-LETI in France.
|}
*

To address the increasing need for Reliability (ageing) simulation the CMC nominated the OMI Interface<ref>{{Cite web |last=Shaw |first=Colin |date=December 17, 2015 |title=CMC OMI - Open Model Interface |url=https://www.mos-ak.org/washington_dc_2015/presentations/B01_Colin_Shaw_MOS-AK_Washington_DC_2015.pdf}}</ref> as the new EDA vendor independent solution for ageing simulations. Technically the Interface is very close the TMI2 Interface developed by [[TSMC]]. The standardization will allow Silicon Foundries to develop a common set of aging models that will work with all significant analog simulators.

The CMC also has released a Verilog-A code recommended best practices document (“CMC Policy on Standardization of Verilog-A Model Code”)<ref name=":0" /> and a Verilog-A Linter program called VAMPyRE [https://github.com/analogdevicesinc/vampyre (Github link)] which can be freely accessed to help increase the quality of model code for all model developers worldwide.

The CMC continues to evaluate new models for standardarization.  New models are submitted to the Coalition, where their technical merits are discussed, and then potential standard models are voted on.

In 2025, the CMC has started a new initiative and is setting up and running the first International Compact Modeling Conference (ICMC),<ref>{{Cite web |title=International Compact Modeling Conference (ICMC) |url=https://www.conferencelists.org/event/international-compact-modeling-conference-icmc/#google_vignette |access-date=2025-05-09 |website=International Conference Lists |language=en-US}}</ref> to be held on June 26-June 27 in San Francisco, co-located with the DAC 2025 conference.

== See also ==
* [[Electronic circuit simulation]]

== References ==
{{Reflist}}

== External links ==
* [http://www.si2.org/cmc_members_list.php Member list at CMC website]
* [https://www.si2.org/cmc_index.php Site map of CMC website including links to working groups]

[[Category:Transistor modeling]]
[[Category:Electronic engineering]]