View source for C to HDL

{{Short description|Conversion of C-like programs into hardware description languages}}
'''C to HDL''' tools convert [[C (programming language)|C language]] or [[List of C-family programming languages|C-like]] [[source code|computer code]] into a [[hardware description language]] (HDL) such as [[VHDL]] or [[Verilog]].  The converted code can then be [[logic synthesis|synthesized]] and [[Translator (computing)|translated]] into a hardware device such as a [[field-programmable gate array]].  Compared to [[software]], equivalent designs in [[Computer hardware|hardware]] consume less power (yielding higher [[performance per watt]]) and execute faster with lower [[Latency (engineering)|latency]], more [[Parallel computing|parallelism]] and higher [[Throughput#Integrated Circuits|throughput]].  However, [[Systems design|system design]] and [[functional verification]] in a hardware description language can be tedious and time-consuming, so systems engineers often write [[Critical section|critical modules]] in HDL and other [[Modularity|modules]] in a [[High-level programming language|high-level language]] and synthesize these into HDL through C to HDL or [[high-level synthesis]] tools.

'''C to {{Abbr|RTL|register transfer level}}''' is another name for this methodology.  RTL refers to the [[register transfer level]] representation of a program necessary to implement it in logic.

== History==
Early development on C to HDL was done by Ian Page, Charles Sweeney and colleagues at [[University of Oxford|Oxford University]] in the 1990s who developed the [[Handel-C]] language.  They [[Commercialization|commercialized]] their research by forming Embedded Solutions Limited (ESL) in 1999 which was renamed Celoxica in September 2000.  In 2008, the embedded systems departments of Celoxica was sold to Catalytic for $3 million and which later merged to become Agility Computing.<ref>{{Cite news|url=http://www.eetimes.com/news/semi/rss/showArticle.jhtml?articleID=205208538&cid=RSSfeed_eetimes_semiRSS|title=Celoxica sells EDA business to Catalytic for $3 million|last=Clarke|first=Peter|date=1 April 2008|work=EE Times}}</ref>  In January 2009, [[Mentor Graphics]] acquired Agility's C synthesis assets.<ref>{{cite web |url=http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=212902054|title=Mentor buys Agility's C synthesis assets|author= Dylan McGrath|date=22 January 2009|publisher=[[EETimes.com]]}}</ref>  Celoxica continues to trade concentrating on [[hardware acceleration]] to process transactions in the financial sector and other [[Industry (economics)|industries]].<ref>{{cite web|url=http://celoxica.com/aboutus/company.html|title=Celoxica Ltd 'About Us'|author=Celoxica Ltd|date=22 January 2011|publisher=[[Celoxica.com]]|access-date=22 January 2011|archive-url=https://web.archive.org/web/20110116031419/http://www.celoxica.com/aboutus/company.html|archive-date=16 January 2011|url-status=dead}}</ref>

== Applications ==
C to HDL techniques are most commonly applied to [[Application software|applications]] that have unacceptably high [[Run-time complexity|execution times]] on existing general-purpose [[supercomputer]] architectures.  Examples include [[bioinformatics]], [[computational fluid dynamics]] (CFD),{{clarify|date=February 2009}} financial processing, and oil and gas survey data analysis.  [[Embedded system|Embedded applications]] requiring [[High Performance Computing|high performance]] or [[Real-time operating system|real-time]] [[data processing]] are also an area of use.  [[System on a chip|System-on-chip]] (SoC) design may also take advantage of C to HDL techniques.

C-to-VHDL compilers are very useful for large designs or for implementing code that might change in the future.  Designing a large application entirely in HDL may be very difficult and time-consuming; the abstraction of a high level language for such a large application will often reduce total development time.  Furthermore, an application coded in HDL will almost certainly be more difficult to modify than one coded in a higher level language.  If the designer needs to add new functionality to the application, adding a few lines of C code will almost always be easier than remodeling the equivalent HDL code.

[[Flow to HDL]] tools have a similar aim, but with [[Dataflow programming|flow]] rather than C-based design.

== Example tools ==
*[https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/smarthls-compiler SmartHLS] (originally LegUp), ANSI C to Verilog tool developed by [[Microchip Technology]], based on LLVM compiler.
*[https://www.cl.cam.ac.uk/~djg11/cvtovpage-real CBG CtoV] A tool developed 1995-99 by DJ Greaves ([[University of Cambridge]]) that instantiated RAMs and interpreted various [[SystemC]] constructs and datatypes.
*C-to-Verilog tool ([[No instruction set computing|NISC]]) from [[University of California, Irvine]]
*[http://www.altium.com/Products/AltiumDesigner/ Altium Designer 6.9 and 7.0] (a.k.a. Summer 08) from [[Altium]]
*[https://www.intel.com/content/www/us/en/programmable/b/nios2-c2h.html Nios II C-to-Hardware Acceleration Compiler] from [[Altera]]
*[[Catapult C]] tool from  [[Mentor Graphics]]
*Cynthesizer from [[Forte Design Systems]]
*[[SystemC]] from [http://www.celoxica.com/ Celoxica (defunct)]
*[[Handel-C]] from [http://www.celoxica.com/ Celoxica (defunct)]
*[[DIME-C]] from [[Nallatech]]
*[[Impulse C]] from [http://www.impulsec.com/ Impulse Accelerated Technologies]
*[https://www.fpga-cores.com/instant-soc/ Instant-SoC] from [https://www.fpga-cores.com/ FPGA-Cores]
*[[FpgaC]] which is an open source initiative
*[[SA-C programming language]]
* Cascade (C to RTL synthesizer) from CriticalBlue
*[[Mitrion-C]] from [[Mitrionics]]
*SPARK (a C-to-VHDL) from [[University of California, San Diego]]<ref>{{cite web|url=http://mesl.ucsd.edu/spark/|title=SPARK: High-Level Synthesis using Parallelizing Compiler Techniques|access-date=2020-07-11|archive-date=2009-10-24|archive-url=https://web.archive.org/web/20091024222430/http://mesl.ucsd.edu/spark/|url-status=dead}}</ref>
*VLSI/VHDL CAD Group Index of Useful Tools from [[Case Western Reserve University]]<ref>{{cite web|url=http://bear.cwru.edu/tools.html|title=VLSI CAD Group Index of Useful Tools|access-date=2017-07-28|archive-date=2011-07-19|archive-url=https://web.archive.org/web/20110719183022/http://bear.cwru.edu/tools.html|url-status=bot: unknown}}</ref>
*[[MyHDL]] is a Python-subset compiler and simulator to [[VHDL]] and [[Verilog]]<ref>{{cite web |url=http://www.myhdl.org/ |title=Home |website=myhdl.org}}</ref>

== See also ==
* [[Comparison of EDA Software]]
* [[Electronic design automation]] (EDA)
* [[High-level synthesis]]
* [[Silicon compiler]]
*[[Hardware acceleration]]

== References ==
<references/>

== External links ==
*[http://www.ddj.com/dept/cpp/197004413 A good article on Dr Dobbs Journal about ImpulseC.]
*[http://www.cse.clrc.ac.uk/disco/publications/FPGA_overview_2.0.pdf An overview of flows by Daresbury Labs.]{{Dead link|date=June 2019 |bot=InternetArchiveBot |fix-attempted=yes }}
*[http://web.comlab.ox.ac.uk/oucl/work/christian.peter/overview_handelc.html An Overview of Hardware Compilation and the Handel-C language.]
*[https://web.archive.org/web/20070216180902/http://www.xilinx.com/products/design_tools/logic_design/advanced/esl/index.htm Xilinx's ESL initiative, some products listed and C to VHDL tools.]
*[http://www.altium.com/Evaluate/DEMOcenter/#,11,0,1,3 Altium's C-to-Hardware Compiler overview.]
*[http://www.altera.com/literature/wp/wp-aghrdwr.pdf Altera's Nios II C2H Acceleration Compiler White Paper.]

{{Programmable Logic}}
{{Hardware acceleration}}

[[Category:Hardware description languages]]
[[Category:Program transformation]]
[[Category:Hardware acceleration]]