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{{Short description|Microcontroller machine language}}
{{main article|Atmel AVR}}

The  '''Atmel AVR instruction set''' is the [[machine language]] for the [[Atmel AVR]], a [[modified Harvard architecture]] 8-bit [[Reduced instruction set computer|RISC]] single chip [[microcontroller]] which was developed by [[Atmel]] in 1996.  The AVR was one of the first microcontroller families to use on-chip [[flash memory]] for program storage.

== Processor registers ==
{| class="infobox" style="font-size:88%;width:38em;"
|-
|+ Atmel AVR registers
|-
|
{| style="font-size:88%;"
|-
| style="width:10px; text-align:center;"| <sup>2</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>2</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|-
|colspan="21" | '''General purpose registers''' <br />
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R1
| style="text-align:center;" colspan="8"| R0
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R3
| style="text-align:center;" colspan="8"| R2
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R5
| style="text-align:center;" colspan="8"| R4
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R7
| style="text-align:center;" colspan="8"| R6
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R9
| style="text-align:center;" colspan="8"| R8
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R11
| style="text-align:center;" colspan="8"| R10
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R13
| style="text-align:center;" colspan="8"| R12
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R15
| style="text-align:center;" colspan="8"| R14
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R17
| style="text-align:center;" colspan="8"| R16
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R19
| style="text-align:center;" colspan="8"| R18
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R21
| style="text-align:center;" colspan="8"| R20
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R23
| style="text-align:center;" colspan="8"| R22
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R25
| style="text-align:center;" colspan="8"| R24
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R27
| style="text-align:center;" colspan="8"| R26
| style="background:white; color:black;"| '''X''' (pointer)
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R29
| style="text-align:center;" colspan="8"| R28
| style="background:white; color:black;"| '''Y''' (pointer)
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| R31
| style="text-align:center;" colspan="8"| R30
| style="background:white; color:black;"| '''Z''' (pointer)
|- 
|colspan="21" | '''Stack pointer''' <br />
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| SPH
| style="text-align:center;" colspan="8"| SPL
| style="background:white; color:black;"| [[Call stack|'''S'''tack '''P'''ointer]]
|-
|colspan="21" | '''Program counter''' <br />
|- style="background:silver;color:black"
| style="text-align:center;" colspan="22"| PC
| style="background:white; color:black;"| [[Program counter|'''P'''rogram '''C'''ounter]]
|-
|colspan="21" | '''Extended memory''' <br />
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="14"| &nbsp;
| style="text-align:center;" colspan="8"| RAMPD
| style="background:white; color:black;"| Extended direct
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="14"| &nbsp;
| style="text-align:center;" colspan="8"| RAMPX
| style="background:white; color:black;"| Extended X
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="14"| &nbsp;
| style="text-align:center;" colspan="8"| RAMPY
| style="background:white; color:black;"| Extended Y
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="14"| &nbsp;
| style="text-align:center;" colspan="8"| RAMPZ
| style="background:white; color:black;"| Extended Z
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="14"| &nbsp;
| style="text-align:center;" colspan="8"| EIND
| style="background:white; color:black;"| Extended indirect
|-
|colspan="21" | '''Status register'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="14"| &nbsp;
| style="text-align:center;"| [[Interrupt flag|I]]
| style="text-align:center;"| T
| style="text-align:center;"| [[Half-carry flag|H]]
| style="text-align:center;"| [[Sign flag|S]]
| style="text-align:center;"| [[Overflow flag|V]]
| style="text-align:center;"| [[Sign flag|N]]
| style="text-align:center;"| [[Zero flag|Z]]
| style="text-align:center;"| [[Carry flag|C]]
| style="background:white; color:black" | SREG
|}
|}
There are 32 general-purpose 8-bit registers, R0–R31. All arithmetic and logic operations operate on those registers; only load and store instructions access RAM.

A limited number of instructions operate on 16-bit register pairs. The lower-numbered register of the pair holds the least significant bits and must be even-numbered. The last three register pairs are used as pointer registers for memory addressing. They are known as X (R27:R26), Y (R29:R28) and Z (R31:R30). Postincrement and predecrement addressing modes are supported on all three. Y and Z also support a six-bit positive displacement.

Instructions which allow an immediate value are limited to registers R16–R31 (8-bit operations) or to register pairs R25:R24–R31:R30 (16-bit operations ADIW and SBIW). Some variants of the MUL operation are limited to eight registers, R16 through R23.

===Special purpose registers===
In addition to these 32 general-purpose registers, the CPU has a few special-purpose registers:
* PC: 16- or 22-bit program counter
* SP: 8- or 16-bit stack pointer
* SREG: 8-bit status register
* RAMPX, RAMPY, RAMPZ, RAMPD and EIND: 8-bit segment registers that are prepended to 16-bit addresses in order to form 24-bit addresses; only available in parts with large address spaces.

===Status register===
The status register bits are:
#<li value=0> C [[Carry flag]]. This is a borrow flag on subtracts.</li>
# Z [[Zero flag]]. Set when an arithmetic result is zero, and cleared when it is non-zero.
# N [[Negative flag]]. Set to a copy of the most significant bit of an arithmetic result.
# V [[Overflow flag]]. Set in case of two's complement overflow.
# S Sign flag. Unique to AVR, this is always N⊕V, and shows the true sign of a comparison.
# H [[Half-carry flag]]. This is an internal carry from additions and is used to support [[Binary-coded decimal|BCD]] arithmetic.
# T Bit copy. Special bit load and bit store instructions use this bit.
# I [[Interrupt flag]]. Set when interrupts are enabled.

There are two special cases which exist to facilitate multi-byte arithmetic:
* The <code>INC</code> and <code>DEC</code> instructions do ''not'' modify the carry flag, so they may be used to loop over [[arbitrary-precision arithmetic]] operands.<ref name="isa_manual">{{cite web |url=https://ww1.microchip.com/downloads/en/DeviceDoc/AVR-InstructionSet-Manual-DS40002198.pdf |title=AVR Instruction Set Manual |date=November 2016 |publisher=Atmel |id=Atmel-0856L}}</ref>{{Rp|84,101}}
* The <code>CPC</code>, <code>SBC</code> and <code>SBCI</code> (compare/subtract with carry) instructions do ''not'' set the Z flag when the result is zero, but only clear it if the result is non-zero.{{r|isa_manual|p=79,147,149}}  For ''fixed'' precision multi-byte comparisons, implemented with an [[Loop unrolling|unrolled]] <code>CP; CPC; CPC; CPC</code> sequence, this produces a zero flag which is set only if the ''entire'' difference is zero.

== Addressing ==
The following address spaces are available:
* The general purpose registers are addressed by their numbers (0–31), although the full 5-bit number is not stored in instructions that can only operate on a subset of those registers.
* I/O registers have a dedicated 6-bit address space, the lower half of which is bit-addressable; some parts have I/O registers outside this address space, which are called "extended I/O" and are only accessible as [[memory-mapped I/O]] in the data address space.
* The data address space maps the 32 general-purpose registers, all the I/O registers (including those also accessible through the I/O address space), and the RAM; it can be addressed either directly or indirectly through the X, Y and Z pointer registers, prepended if necessary by RAMPX, RAMPY and RAMPZ respectively.
* Program memory ([[Flash memory|flash]]) has a separate address space, addressed as 16-bit words for the purpose of fetching instructions
* For the purpose of fetching constant data, program memory is addressed bytewise through the Z pointer register, prepended if necessary by RAMPZ.
* The [[EEPROM]] is memory-mapped in some devices; in others, it is not directly addressable and is instead accessed through address, data and control I/O registers.
* The general purpose registers, the status register and some I/O registers are bit-addressable, with bit 0 being the least significant and bit 7 the most significant.

The first 64 I/O registers are accessible through both the I/O and the data address space. They have therefore two different addresses. These are usually written as "{{mono|0x00}} ({{mono|0x20}})" through "{{mono|0x3F}} ({{mono|0x5F}})", where the first item is the I/O address and the second, in parentheses, the data address.

The special-purpose CPU registers, with the exception of PC, can be accessed as I/O registers. Some registers (RAMPX, RAMPY) may not be present on machines with less than 64 [[KiB]] of addressable memory.

{| class="wikitable"
! Register !! I/O address !! Data address
|-
| SREG     || {{mono|0x3F}}        || {{mono|0x5F}}
|-
| SP       || {{mono|0x3E}}:{{mono|0x3D}}   || {{mono|0x5E}}:{{mono|0x5D}}
|-
| EIND     || {{mono|0x3C}}        || {{mono|0x5C}}
|-
| RAMPZ    || {{mono|0x3B}}        || {{mono|0x5B}}
|-
| RAMPY    || {{mono|0x3A}}        || {{mono|0x5A}}
|-
| RAMPX    || {{mono|0x39}}        || {{mono|0x59}}
|-
| RAMPD    || {{mono|0x38}}        || {{mono|0x58}}
|}

A typical ATmega memory map may look like:

{| class="wikitable"
! Data address    !! I/O address !! Contents
|-
| {{mono|0x0000}} – {{mono|0x001F}} ||             || Registers R0 – R31
|-
| {{mono|0x0020}} – {{mono|0x003F}} || {{mono|0x00}} – {{mono|0x1F}} || I/O registers (bit-addressable)
|-
| {{mono|0x0040}} – {{mono|0x005F}} || {{mono|0x20}} – {{mono|0x3F}} || I/O registers (not bit-addressable)
|-
| {{mono|0x0060}} – {{mono|0x00FF}} ||             || Extended I/O registers (memory-mapped I/O only)
|-
| {{mono|0x0100}} – {{mono|RAMEND}} ||             || Internal SRAM
|}

where RAMEND is the last RAM address. In parts lacking extended I/O the RAM would start at {{mono|0x0060}}.

== Instruction timing ==
Arithmetic operations work on registers R0–R31 but not directly on RAM and take one clock cycle, except for multiplication and word-wide addition (ADIW and SBIW) which take two cycles.

RAM and I/O space can be accessed only by copying to or from registers. Indirect access (including optional postincrement, predecrement or constant displacement) is possible through registers X, Y, and Z. All accesses to RAM takes two clock cycles. Moving between registers and I/O is one cycle. Moving eight or sixteen bit data between registers or constant to register is also one cycle. Reading program memory (LPM) takes three cycles.

== Instruction list ==
Instructions are one 16-bit long word, save for those including a 16-bit or 22-bit address, which take two words.

There are two types of conditional branches: jumps to address and skips. Conditional branches (BRxx) can test an ALU flag and jump to specified address. Skips (SBxx) test an arbitrary bit in a register or I/O and skip the next instruction if the test was true.

In the following:
* Rd and Rr are registers in the range R0–R31
* Rdh and Rrh are registers in the range R16–R31 (high half)
* Rdq and Rrq are registers in the range R16–R23 (one quarter of the register file)
* Rp is a register pair R25:R24, R27:R26 (X), R29:R28 (Y) or R31:R30 (Z)
* XYZ is a pointer register, either X or Y or Z
* YZ is a pointer register, either Y or Z
* s is a bit number in the status register (0 = C, 1 = Z, etc., see the list above)
* b is a bit number in a general-purpose or I/O register (0 = least significant, 7 = most significant)
* K6 is a 6-bit immediate ''unsigned'' constant (range: 0–63)
* K8 is an 8-bit immediate constant; since it is used only in 8-bit operations, its signedness is irrelevant
* IO5 is a 5-bit I/O address covering the bit-addressable part of the I/O address space, i.e. the lower half (range: 0–31)
* IO6 is a 6-bit I/O address covering the full I/O address space (range: 0–63)
* D16 is a 16-bit data address covering 64&nbsp;[[KiB]]; in parts with more than 64&nbsp;KiB data space, the contents of the RAMPD segment register is prepended
* P22 is a 22-bit program address covering 2<sup>22</sup> 16-bit words (i.e. 8&nbsp;[[MiB]])
* S7 and S12 are 7-bit and 12-bit ''signed'' displacements, in units of words, relative to the program address stored in the program counter

{| class="wikitable"
|+ AVR instruction set
|-
! Arithmetic
! Bit & Others
! Transfer
! Jump
|-
|valign=top rowspan=5|{{#tag:syntaxhighlight|
ADD  Rd, Rr
ADC  Rd, Rr
ADIW Rp+1:Rp, K6

SUB  Rd, Rr
SUBI Rdh, K8
SBC  Rd, Rr
SBCI Rdh, K8
SBIW Rp+1:Rp, K6

INC  Rd
DEC  Rd

AND  Rd, Rr
ANDI Rdh, K8
OR   Rd, Rr
ORI  Rdh, K8
<!--
<S> CLR  Rd </S> (EOR)
<S> SER  Rdh </S> (LDI)
<S> SBR  Rdh, K8 </S> (ORI)
<S> CBR  Rdh, K8 </S> (ANDI)
<S> TST  Rd </S> (AND)
!-->
COM  Rd
NEG  Rd
CP   Rd, Rr
CPC  Rd, Rr
CPI  Rdh, K8
SWAP Rd
<!--
<S> LSL  Rd </S> (ADD)
<S> ROL  Rd </S> (ADC)
!-->
LSR  Rd
ROR  Rd
ASR  Rd

MUL    Rd, Rr
MULS   Rdh, Rrh
MULSU  Rdq, Rrq
FMUL   Rdq, Rrq
FMULS  Rdq, Rrq
FMULSU Rdq, Rrq
|lang="nasm"|style=font-size:95%}}
|valign=top rowspan=5|{{#tag:syntaxhighlight|
BSET s
BCLR s
SBI  IO5, b
CBI  IO5, b
BST  Rd, b
BLD  Rd, b

NOP
BREAK
SLEEP
WDR|lang="nasm"|style=font-size:95%}}
|valign=top rowspan=5|{{#tag:syntaxhighlight|
MOV  Rd, Rr
MOVW Rd+1:Rd, Rr+1:Rr

IN   Rd, IO6
OUT  IO6, Rr

PUSH Rr
POP  Rr

LDI  Rdh, K8
LDS  Rd, D16

LD   Rd, X
LDD  Rd, YZ+K6
LD   Rd, -XYZ
LD   Rd, XYZ+

STS  D16, Rr

ST   X, Rr
STD  YZ+K6, Rr
ST   -XYZ, Rr
ST   XYZ+, Rr

LPM
LPM  Rd, Z
LPM  Rd, Z+
ELPM
ELPM Rd, Z
ELPM Rd, Z+

SPM|lang="nasm"|style=font-size:95%}}
|valign=top|{{#tag:syntaxhighlight|
RJMP S12
IJMP
EIJMP
JMP  P22|lang="nasm"|style=font-size:95%}}
|-
! Call
|-
|valign=top|{{#tag:syntaxhighlight|
RCALL S12
ICALL
EICALL
CALL  P22

RET
RETI|lang="nasm"|style=font-size:95%}}
|-
! Branch
|-
|valign=top|{{#tag:syntaxhighlight|
CPSE Rd, Rr

SBRC Rr, b
SBRS Rr, b

SBIC IO5, b
SBIS IO5, b

BRBC s, S7
BRBS s, S7|lang="nasm"|style=font-size:95%}}
|}

== Instruction set inheritance ==

Not all instructions are implemented in all [[Atmel AVR]] controllers. This is the case of the instructions performing multiplications, extended loads/jumps/calls, long jumps, and power control.

The optional instructions may be grouped into three categories:
* core cpu (computation) features, added on more capable CPU cores
* memory addressing features, added on all models with memory large enough to require them
* optional features, a few peripherals that may or may not be present on a particular model.
While higher-end processors tend to have both more capable cores and more memory, the presence of one does not guarantee the presence of the other.

===Core CPU instructions===
Beginning with the original "classic" core, enhancements are organized into the following levels, each of which includes all the preceding:
# The "Classic" core has only the zero-operand form of the <code>LPM</code> instruction, which is equivalent to <code>LPM r0,Z</code>.
# "Classic plus" adds the <code>MOVW</code> instruction for moving register pairs, and the more general form of the LPM instruction (<code>LPM Rd,Z</code> and <code>LPM Rd,Z+</code>) which permit an arbitrary destination register and auto-increment of the Z pointer.
# "Enhanced" cores add the multiply instructions.
# The XMEGA cores do not add new instructions ''per se'', but make some significant changes:
#* The memory map is reorganized, eliminating memory-mapping of the processor register file (so I/O ports begin at RAM address 0) and expanding the I/O port range.  Now the first 4K is special function registers, the second 4K is data flash, and normal RAM begins at 8K.
#* It is not necessary to explicitly disable interrupts before adjusting the stack pointer registers (SPL and SPH); any write to SPL automatically disables interrupts for 4 clock cycles to give time for SPH to be updated.<!--Technically, until the next I/O write (presumably SPH) or 4 cycles, whichever comes first-->
#* Other multi-byte registers are provided with shadow registers to enable [[Atomic operation|atomic]] read and write.  When the lowest-order byte is read, the higher-order bytes are copied to the shadow registers, so reading them later produces a [[snapshot (computer storage)|snapshot]] of the register at the time of the first read.  Writes to low-order bytes are buffered until the highest-order byte is written, upon which the entire multi-byte register is updated atomically. 
# Later XMEGA cores (specifically, the B, C, and AU models such as the ATxmega16A4U, but ''not'' the earlier A, D and E models such as the ATxmega16D4) add four atomic [[read-modify-write]] instructions: exchange (<code>XCH</code>), load-and-set, load-and-clear, and load-and-toggle.<!--This is from the avr-mcus.def file in the GCC sources, and doesn't match the data sheets, but Atmel redesigned those in 2016 and introduced a lot of errors; many have changelogs mentioning "deleted DES instruction" suggesting they cut & pasted the instruction list and didn't delete unsupported instructions properly. -->  These help coordinate with [[direct memory access]] peripherals, notably a [[USB]] controller.

Less capable than the "classic" CPU cores are two subsets: the "AVR1" core, and the "AVR tiny".  Confusingly, "ATtiny" branded processors have a variety of cores, including AVR1 (ATtiny11, ATtiny28), classic (ATtiny22, ATtiny26), classic+ (ATtiny24) and AVRtiny (ATtiny20, ATtiny40).

The AVR1 subset was not popular and no new models have been introduced since 2000.  It omits all RAM except for the 32 registers mapped at address 0–31 and the I/O ports at addresses 32–95.  The stack is replaced by a 3-level hardware stack, and the <code>PUSH</code> and <code>POP</code> instructions are deleted.  All 16-bit operations are deleted, as are <code>IJMP</code>, <code>ICALL</code>, and all load and store addressing modes except indirect via Z.

A second, more successful attempt to subset the AVR instruction set is the "AVR tiny" core.

The most significant change is that the AVRtiny core omits registers R0–R15.  The registers are also not memory-mapped, with I/O ports from 0–63 and general-purpose RAM beginning at address 64.  The 16-bit arithmetic operations (<code>ADIW</code>, <code>SBIW</code>) are omitted, as are the load/store with displacement addressing modes (<code>Y+d</code>, <code>Z+d</code>), but the predecrement and postincrement addressing modes are retained.  The <code>LPM</code> instruction is omitted; instead program ROM is mapped to the data address space and may be accessed with normal load instructions.

Finally, the AVRtiny core deletes the 2-word <code>LDS</code> and <code>STS</code> instructions for direct RAM addressing, and instead uses the opcode space previously assigned to the load/store with displacement instructions for new 1-word <code>LDS</code> and <code>STS</code> instructions which can access the first 128 locations of general-purpose RAM, addresses 0x40 to 0xBF.  (The <code>IN</code> and <code>OUT</code> instructions provide direct access to I/O space from 0 to 0x3F.)

===Memory addressing instructions===
The smallest cores have ≤256 bytes of data address space (meaning ≤128 bytes of RAM after I/O ports and other reserved addresses are removed) and ≤8192 bytes (8 KiB) of program ROM.  These have only an 8-bit stack pointer (in SPL), and only support the 12-bit relative jump/call instructions <code>RJMP</code>/<code>RCALL</code>.  (Because the AVR program counter counts 16-bit words, not bytes, a 12-bit offset is sufficient to address 2<sup>13</sup> bytes of ROM.)

Additional memory addressing capabilities are present as required to access available resources:
# Models with >256 bytes of data address space (≥256 bytes of RAM) have a 16-bit stack pointer, with the high half in the SPH register.
# Models with >8 KiB of ROM add the 2-word (22-bit) <code>JUMP</code> and <code>CALL</code> instructions.  (Some early models suffer an [[erratum]] if a skip instruction is followed by a 2-word instruction.)
# Models with >64 KiB of ROM add the <code>ELPM</code> instruction and corresponding RAMPZ register.  <code>LPM</code> instructions zero-extend the ROM address in Z; <code>ELPM</code> instructions prepend the RAMPZ register for high bits.  This is not the same thing as the more general <code>LPM</code> instruction; there exist "classic" models with only the zero-operand form of <code>ELPM</code> (ATmega103 and at43usb320).  When auto-increment is available (most models), it updates the entire 24-bit address including RAMPZ.
# (Rare) models with >128 KiB of ROM have a 3-byte program counter.  Subroutine calls and returns use an additional byte of stack space, there is a new EIND register to provide additional high bits for indirect jumps and calls, and there are new extended instructions <code>EIJMP</code> and <code>EICALL</code> which use EIND:Z as the destination address.  (The previous <code>IJMP</code> and <code>ICALL</code> instructions use zero-extended Z.)
# (Rare) models with >64 KiB of RAM address space extend the 16-bit RAM addressing limits with RAMPX, RAMPY, RAMPZ and RAMPD registers.  These provide additional high bits for addressing modes which use the X, Y, or Z register pairs, respectively, or the direct addressing instructions <code>LDS</code>/<code>STS</code>.  Unlike ROM access, there are no distinct "extended" instructions; instead the RAMP registers are used unconditionally.

===Optional feature instructions===
Three instructions are present only on models which have the corresponding hardware facility
* <code>SPM</code> for storing to flash ROM, is present only on processors with flash ROM (most of them)
* <code>BREAK</code> for invoking the on-chip debugger, is omitted on some small models without on-chip debugger support
* <code>DES</code> for performing [[Data Encryption Standard]] rounds, is present on XMEGA models with DES accelerator support

Architectures other than AVR1 are named according to avr-libc conventions.<ref name="avr-libc-gnu-archname">{{cite web|title=Using the GNU tools|url=https://www.nongnu.org/avr-libc/user-manual/using_tools.html|website=AVR Libc Manual|accessdate=6 May 2018}}</ref>

{| class="wikitable"
! Family
! Members
! Arithmetic
! Branches
! Transfers
! Bit-Wise
|- style="vertical-align:top;"
! scope=row | Minimal AVR1 Core
| {{ublist|AT90S1200|ATtiny11|ATtiny12|ATtiny15|ATtiny28}}
| {{ublist|item_style=font-family:monospace;|ADD (LSL)|ADC (ROL)|SUB |SUBI|SBC|SBCI|AND (TST)|ANDI (CBR)|OR|ORI (SBR)|EOR (CLR)|COM|NEG|INC|DEC}}
| {{ublist|item_style=font-family:monospace;|RJMP|RCALL|RET|RETI|CPSE|CP|CPC|CPI|SBRC|SBRS|SBIC|SBIS|BRBS (BRCS,&ZeroWidthSpace;BRLO,&ZeroWidthSpace;BREQ,&ZeroWidthSpace;BRMI,&ZeroWidthSpace;BRVS,&ZeroWidthSpace;BRLT,&ZeroWidthSpace;BRHS,&ZeroWidthSpace;BRTS,&ZeroWidthSpace;BRIE)|BRBC (BRCC,&ZeroWidthSpace;BRSH,&ZeroWidthSpace;BRNE,&ZeroWidthSpace;BRPL,&ZeroWidthSpace;BRVC,&ZeroWidthSpace;BRGE,&ZeroWidthSpace;BRHC,&ZeroWidthSpace;BRTC,&ZeroWidthSpace;BRID)}}
| {{ublist|item_style=font-family:monospace;|LD|ST|MOV|LDI (SER)|IN|OUT|{{mono|LPM}} (not in AT90S1200)|item7_style=font-family:unset;}}
| {{ublist|item_style=font-family:monospace;|SBI|CBI|LSR|ROR|ASR|SWAP|BSET (SEC, SEZ, SEN, SEV, SES, SEH, SET, SEI)|BCLR (CLC, CLZ, CLN, CLV, CLS, CLH, CLT, CLI)|BST|BLD|NOP|SLEEP|WDR}}
|- style="vertical-align:top;"
! scope=row | Classic Core up to 8K Program Space ("AVR2")
| {{ublist|AT90S2313|AT90S2323|ATtiny22|AT90S2333|AT90S2343|AT90S4414|AT90S4433|AT90S4434|AT90S8515|AT90C8534|AT90S8535|ATtiny26}}
| new instructions: {{ublist|item_style=font-family:monospace;|ADIW|SBIW}}
| new instructions: {{ublist|item_style=font-family:monospace;|IJMP|ICALL}}
| new instructions: {{ublist|item_style=font-family:monospace;|item1_style=font-family:unset;|{{mono|LD}} (now 9 modes)|LDD|LDS|item4_style=font-family:unset;|{{mono|ST}} (9 modes)|STD|STS|PUSH|POP}}
|  {{CNone|(nothing new)}}
|- style="vertical-align:top;"
! scope=row | AVR2, with MOVW and LPM instructions ("AVR2.5")
|{{plainlist|
* ATa5272
* ATtiny13/a
* ATtiny2313/a
* ATtiny24/a
* ATtiny25
* ATtiny261/a
* ATtiny4313
* ATtiny43u
* ATtiny44/a
* ATtiny45
* ATtiny461/a
* ATtiny48
* ATtiny828
* ATtiny84/a
* ATtiny85
* ATtiny861/a
* ATtiny87
* ATtiny88
}}
|{{CNone|(nothing new)}}
|{{CNone|(nothing new)}}
|new instructions:
{{plainlist|
* {{mono|MOVW}}
* {{mono|LPM (Rx, Z[+])}}
* {{mono|SPM}}
}}
|{{CNone|(nothing new)}}
|- style="vertical-align:top;"
! scope=row |  Classic Core with up to 128K ("AVR3")
| {{ublist|ATmega103|ATmega603|AT43USB320|AT76C711}}
| {{CNone|(nothing new)}}
| new instructions:{{ublist|item_style=font-family:monospace;|JMP|CALL}}
| new instructions:{{ublist|{{mono|ELPM}} (in "AVR3.1")}}
| {{CNone|(nothing new)}}
|- style="vertical-align:top;"
! scope=row |  Enhanced Core with up to 8K ("AVR4")
| {{ublist|ATmega8|ATmega83|ATmega85|ATmega8515}}
| new instructions:{{ublist|item_style=font-family:monospace;|MUL|MULS|MULSU|FMUL|FMULS|FMULSU<ref>Atmel. [http://www.atmel.com/Images/doc1631.pdf Application Note "AVR201: Using the AVR Hardware Multiplier"]. 2002. quote: "The megaAVR is a series of new devices in the AVR RISC Microcontroller family that includes, among other new enhancements, a hardware multiplier."</ref>}}
| {{CNone|(nothing new)}}
| new instructions:{{ublist|{{mono|MOVW}}|{{mono|LPM}} (3 modes)|{{mono|SPM}}}}
| {{CNone|(nothing new)}}
|- style="vertical-align:top;"
! scope=row |  Enhanced Core with up to 128K ("AVR5", "AVR5.1")
| {{ublist|ATmega16|ATmega161|ATmega163|ATmega32|ATmega323|ATmega64|ATmega128|AT43USB355|[[Atmel At94k|AT94 (FPSLIC)]]|AT90CAN series|AT90PWM series|ATmega48|[[ATmega88]]|ATmega168|ATmega162|ATmega164|ATmega324|[[ATmega328]]|ATmega644|ATmega165|ATmega169|ATmega325|ATmega3250|ATmega645|ATmega6450|ATmega406}}
| {{CNone|(nothing new)}}
| new instruction: {{ublist|{{mono|ELPMX}} ("AVR5.1")}}
| {{CNone|(nothing new)}}
| new instructions:{{ublist|item_style=font-family:monospace;|BREAK}}
|- style="vertical-align:top;"
! scope=row |  Enhanced Core with up to 4M ("AVR5" and "AVR6")
| {{ublist|ATmega640|ATmega1280|ATmega1281|ATmega2560|ATmega2561}}
| {{CNone|(nothing new)}}
| new instructions:{{ublist|item_style=font-family:monospace;|EIJMP|EICALL}}
| {{CNone|(nothing new)}}
| {{CNone|(nothing new)}}
|- style="vertical-align:top;"
! scope=row |  XMEGA Core ("avrxmega" 2-6)
| ATxmega series
| new instructions:{{ublist|item_style=font-family:monospace;|DES}}
| {{CNone|(nothing new)}}
| new instructions (from second revision silicon - AU,B,C parts) {{ublist|item_style=font-family:monospace;|XCH|LAS|LAC|LAT}}
| {{CNone|(nothing new)}}
|- style="vertical-align:top;"
! scope=row |  Reduced AVRtiny Core ("avrtiny10")
| {{ublist|ATtiny40|ATtiny20|ATtiny10|ATtiny9|ATtiny5|ATtiny4}}
| (Identical to minimal core, except for reduced CPU register set{{note label|reduced|a|a}})
| (Identical to classic core with up to 8K, except for reduced CPU register set{{note label|reduced|a|a}})
| Identical to classic core with up to 8K, with the following exceptions:{{aligned table|cols=2|col1style=font-family:monospace;|LPM|(removed)|LDD|(removed)|STD|(removed)|LD|(also accesses program memory)|LDS
STS|(access is limited to the first 128 bytes of SRAM)||Reduced CPU register set{{note label|reduced|a|a}}}}
| (Identical to enhanced core with up to 128K, except for reduced CPU register set{{note label|reduced|a|a}})
|}
{{note label|reduced|a|a}} Reduced register set is limited to R16 through R31.<ref name="isa_manual"/>

== Instruction encoding ==
Bit assignments:
* {{not a typo|rrrrr / ddddd}} = Source/destination register
* {{not a typo|rrrr / dddd}} = Source/destination register (R16–R31)
* {{not a typo|rrr / ddd}} = Source/destination register (R16–R23)
* RRRR / DDDD = Source/destination register pair (R1:R0–R31:R30)
* pp = Register pair, W, X, Y or Z
* y = Y/Z register pair bit (0=Z, 1=Y)
* u = FMULS(U) unsigned bit (0=FMULS signed, 1=FMULSU unsigned)
* s = Store/load bit (0=LD Rd,mem, 1=ST mem,Rd)
* c = Call/jump (0=jump, 1=call)
* cy = With carry (0=without carry, 1=with carry)
* e = Extend indirect jump/call address with EIND (0=0:Z, 1=EIND:Z)
* q = Extend program memory address with RAMPZ (0=0:Z, 1=RAMPZ:Z)
* {{not a typo|aaaaaa}} = I/O space address
* {{not a typo|aaaaa}} = I/O space address (first 32 only)
* {{not a typo|bbb}} = Bit number (0–7)
* B = Bit value (0 or 1)
* {{not a typo|kkkk}} = 4-bit unsigned constant (DES opcode)
* {{not a typo|kkkkkk}} = 6-bit unsigned constant
* {{not a typo|KKKKKKKK}} = 8-bit constant

The Atmel AVR uses many split fields, where bits are not contiguous in the instruction word. The most commonly encountered is the 5-bit source register field in bits 9 and 3–0.  The most extreme example is the load/store with offset instructions, which break a 6-bit offset into three pieces.

{|class="wikitable" style="text-align:center"
|+Atmel AVR instruction set overview
|-
<!--!width=15pt| 15 !!width=15pt| 14 !!width=15pt| 13 !!width=15pt| 12
!width=15pt| 11 !!width=15pt| 10 !!width=15pt|  9 !!width=15pt|  8
!width=15pt|  7 !!width=15pt|  6 !!width=15pt|  5 !!width=15pt|  4
!width=15pt|  3 !!width=15pt|  2 !!width=15pt|  1 !!width=15pt|  0 !! Instruction-->
! 1<br/>5 || 1<br/>4 || 1<br/>3 || 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 || <br/>8
! <br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Instruction
|-
|colspan=17|
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || align=left| NOP
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 1 ||colspan=4| D D D D ||colspan=4| R R R R ||align=left| MOVW Rd,Rr Move register pair
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 ||colspan=4| d d d d ||colspan=4| r r r r ||align=left| MULS Rd,Rr
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 ||colspan=3| d d d || 0 ||colspan=3| r r r ||align=left| MULSU Rd,Rr
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 0 ||colspan=3| d d d || 1 ||colspan=3| r r r ||align=left| FMUL Rd,Rr
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 ||colspan=3| d d d || u ||colspan=3| r r r ||align=left| FMULS(U) Rd,Rr
|-
|colspan=17|
|-
! 0 || 0 ||colspan=4| opcode || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| Two-operand instructions
|-
| 0 || 0 || 0 || c̅y̅ || 0 || 1 || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| CPC/CP Rd,Rr
|-
| 0 || 0 || 0 || c̅y̅ || 1 || 0 || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| SBC/SUB Rd,Rr
|-
| 0 || 0 || 0 || cy || 1 || 1 || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| ADD/ADC Rd,Rr (LSL/ROL Rd when Rd=Rr)
|-
| 0 || 0 || 0 || 1 || 0 || 0 || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| CPSE Rd,Rr
|-
| 0 || 0 || 1 || 0 || 0 || 0 || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| AND Rd,Rr
|-
| 0 || 0 || 1 || 0 || 0 || 1 || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| EOR Rd,Rr
|-
| 0 || 0 || 1 || 0 || 1 || 0 || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| OR Rd,Rr
|-
| 0 || 0 || 1 || 0 || 1 || 1 || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| MOV Rd,Rr
|-
|colspan=17|
|-
| 0 || 0 || 1 || 1 ||colspan=4| K K K K ||colspan=4| d d d d ||colspan=4| K K K K ||align=left| CPI Rd,K
|-
! 0 || 1 ||colspan=2| opc ||colspan=4| K K K K ||colspan=4| d d d d ||colspan=4| K K K K ||align=left| Register-immediate operations
|-
| 0 || 1 || 0 || c̅y̅ ||colspan=4| K K K K ||colspan=4| d d d d ||colspan=4| K K K K ||align=left| SBCI/SUBI Rd,K
|-
| 0 || 1 || 1 || 0 ||colspan=4| K K K K ||colspan=4| d d d d ||colspan=4| K K K K ||align=left| ORI Rd,K<br/>SBR Rd,K
|-
| 0 || 1 || 1 || 1 ||colspan=4| K K K K ||colspan=4| d d d d ||colspan=4| K K K K ||align=left| ANDI Rd,K<br/>CBR Rd,K
|-
|colspan=17|
|-
| 1 || 0 || k || 0 ||colspan=2| k k || s ||colspan=5| d  d  d  d  d || y ||colspan=3| k k k ||align=left| LDD/STD Rd through Z+k or Y+k
|-
|colspan=17|
|-
! 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d ||colspan=4| opcode ||align=left| Load/store operations
|-
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || 0 || 0 || 0 || 0 ||align=left rowspan=2| LDS Rd,i/STS i,Rd
|-
| colspan=16| 16-Bit immediate SRAM address i
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || 1 || 0 || 0 || 0 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || y || 0 || 0 || 1 ||align=left| LD/ST Rd through Z+/Y+
|-
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || y || 0 || 1 || 0 ||align=left| LD/ST Rd through &minus;Z/&minus;Y
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || y || 0 || 1 || 1 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 0 || 0 ||colspan=5| d d d d d || 0 || 1 || q || 0 ||align=left| LPM/ELPM Rd,Z
|-
| 1 || 0 || 0 || 1 || 0 || 0 || 0 ||colspan=5| d d d d d || 0 || 1 || q || 1 ||align=left| LPM/ELPM Rd,Z+
|-
| 1 || 0 || 0 || 1 || 0 || 0 || 1 ||colspan=5| d d d d d || 0 || 1 || 0 || 0 ||align=left| XCH Z,Rd
|-
| 1 || 0 || 0 || 1 || 0 || 0 || 1 ||colspan=5| d d d d d || 0 || 1 || 0 || 1 ||align=left| LAS Z,Rd
|-
| 1 || 0 || 0 || 1 || 0 || 0 || 1 ||colspan=5| d d d d d || 0 || 1 || 1 || 0 ||align=left| LAC Z,Rd
|-
| 1 || 0 || 0 || 1 || 0 || 0 || 1 ||colspan=5| d d d d d || 0 || 1 || 1 || 1 ||align=left| LAT Z,Rd
|-
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || 1 || 1 || 0 || 0 ||align=left| LD/ST Rd through X
|-
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || 1 || 1 || 0 || 1 ||align=left| LD/ST Rd through X+
|-
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || 1 || 1 || 1 || 0 ||align=left| LD/ST Rd through &minus;X
|-
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || 1 || 1 || 1 || 1 ||align=left| POP/PUSH Rd
|-
|colspan=17|
|-
! 1 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=5| d d d d d || 0 ||colspan=3| opcode ||align=left| One-operand instructions:
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=5| d d d d d || 0 || 0 || 0 || 0 ||align=left| COM Rd
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=5| d d d d d || 0 || 0 || 0 || 1 ||align=left| NEG Rd
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=5| d d d d d || 0 || 0 || 1 || 0 ||align=left| SWAP Rd
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=5| d d d d d || 0 || 0 || 1 || 1 ||align=left| INC Rd
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=5| d d d d d || 0 || 1 || 0 || 0 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=5| d d d d d || 0 || 1 || 0 || 1 ||align=left| ASR Rd
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=5| d d d d d || 0 || 1 || 1 || 0 ||align=left| LSR Rd
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=5| d d d d d || 0 || 1 || 1 || 1 ||align=left| ROR Rd
|-
|colspan=17|
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 0 || B̅ ||colspan=3| b b b || 1 || 0 || 0 || 0 ||align=left| SEx/CLx Status register clear/set bit
|-
|colspan=17|
|-
! 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 ||colspan=4| opcode || 1 || 0 || 0 || 0 ||align=left| Zero-operand instructions
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 || 0 || 0 || 0 || 1 || 0 || 0 || 0 ||align=left| RET 
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || 0 ||align=left| RETI
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 ||colspan=2| ≠ 00 || x || 1 || 0 || 0 || 0 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 1 || 0 || 0 || 0 || 1 || 0 || 0 || 0 ||align=left| SLEEP
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 1 || 0 || 0 || 1 || 1 || 0 || 0 || 0 ||align=left| BREAK
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 1 || 0 || 1 || 0 || 1 || 0 || 0 || 0 ||align=left| WDR 
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 1 || 0 || 1 || 1 || 1 || 0 || 0 || 0 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 1 || 1 || 0 || q || 1 || 0 || 0 || 0 ||align=left| LPM/ELPM  
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 1 || 1 || 1 || 0 || 1 || 0 || 0 || 0 ||align=left| SPM 
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 1 || 1 || 1 || 1 || 1 || 0 || 0 || 0 ||align=left| SPM Z+
|-
|colspan=17|
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || c || 0 || 0 || 0 || e || 1 || 0 || 0 || 1 ||align=left| Indirect jump/call to Z or EIND:Z
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || c ||colspan=3| ≠ 000 || e || 1 || 0 || 0 || 1 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=5| d d d d d || 1 || 0 || 1 || 0 ||align=left| DEC Rd
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 0 ||colspan=4| k k k k || 1 || 0 || 1 || 1 ||align=left| DES round k
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=5|k k k k k || 1 || 1 || c || k ||align=left rowspan=2| JMP/CALL abs22
|-
|colspan=16| k k k k k k k k k k k k k k k k
|-
|colspan=17|
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 1 || 0 ||colspan=2| k k ||colspan=2| p p ||colspan=4| k k k k ||align=left| ADIW Rp,uimm6
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 1 || 1 ||colspan=2| k k ||colspan=2| p p ||colspan=4| k k k k ||align=left| SBIW Rp,uimm6
|-
| 1 || 0 || 0 || 1 || 1 || 0 || B || 0 ||colspan=5| a a a a a ||colspan=3| b b b ||align=left| CBI/SBI a,b (clear/set I/O bit)
|-
| 1 || 0 || 0 || 1 || 1 || 0 || B || 1 ||colspan=5| a a a a a ||colspan=3| b b b ||align=left| SBIC/SBIS a,b (I/O bit test)
|-
| 1 || 0 || 0 || 1 || 1 || 1 || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| MUL, unsigned: R1:R0 = Rr × Rd
|-
|colspan=17|
|-
| 1 || 0 || 1 || 1 || s ||colspan=2| a a ||colspan=5| d d d d d ||colspan=4| a a a a ||align=left| IN/OUT to I/O space
|-
| 1 || 1 || 0 || c ||colspan=12| 12 bit signed offset ||align=left| RJMP/RCALL to PC + simm12
|-
| 1 || 1 || 1 || 0 ||colspan=4| K K K K ||colspan=4| d d d d ||colspan=4| K K K K ||align=left| LDI Rd,K
|-
| 1 || 1 || 1 || 1 || 0 || B̅ ||colspan=7| 7-bit signed offset ||colspan=3| b b b ||align=left| Conditional branch on status register bit
|-
| 1 || 1 || 1 || 1 || 1 || 0 || s ||colspan=5| d d d d d || 0 ||colspan=3| b b b ||align=left| BLD/BST register bit to STATUS.T
|-
| 1 || 1 || 1 || 1 || 1 || 1 || B ||colspan=5| d d d d d || 0 ||colspan=3| b b b ||align=left| SBRC/SBRS skip if register bit equals B
|-bgcolor=lightgray
| 1 || 1 || 1 || 1 || 1 || x || x ||colspan=5| d d d d d || 1 ||colspan=3| b b b || (reserved)
|}

==References==
{{Reflist}}

== External links ==
{{Wikibooks|Embedded Systems|Atmel AVR}}
*GNU Development Environment:
**[http://www.linuxfocus.org/English/November2004/article352.shtml Programming the AVR microcontroller with GCC] by Guido Socher
**[https://web.archive.org/web/20050714015338/http://users.rcn.com/rneswold/avr/ A GNU Development Environment for the AVR Microcontroller] by Rich Neswold
**[https://gcc.gnu.org/onlinedocs/gcc-3.3.5/gcc/AVR-Options.html AVR Options] in GCC-AVR
*[https://github.com/avr-llvm/architecture/blob/master/Instructions/inheritance.md AVR Instruction Set Inheritance] (LLVM note), based on this page and GCC & Binutils code

{{DEFAULTSORT:Atmel Avr Instruction Set}}
[[Category:Atmel microcontrollers]]
[[Category:Instruction set architectures]]