View source for AVR32

{{Short description|32-bit RISC microcontroller architecture}}
{{Multiple issues|
{{primary sources|date=July 2017}}
{{more citations needed|date=July 2017}}
}}

{{Infobox CPU architecture
| name       = AVR32
| designer   = [[Atmel]]
| bits       = 32-bit
| introduced = 
| version    = Rev 2
| design     = RISC
| type       = 
| encoding   = Variable
| branching  = 
| endianness = Big
| extensions = [[Java virtual machine]]
| open       = 
| registers  = 15 <!-- Up to 15 general-purpose 32-bit registers -->
| image      = ATMEL AVR32.jpg
}}

'''AVR32''' is a [[32-bit]] [[RISC]] microcontroller architecture produced by [[Atmel]]. The microcontroller architecture was designed by a handful of people educated at the [[Norwegian University of Science and Technology]], including lead designer Øyvind Strøm and CPU architect Erik Renno in Atmel's Norwegian design center.

Most instructions are executed in a single-cycle. The [[multiply–accumulate]] unit can perform a 32-bit × 16-bit + 48-bit arithmetic operation in two cycles (result latency), issued once per cycle.

It does not resemble the 8-bit [[AVR microcontroller]] family, even though they were both designed at Atmel Norway, in [[Trondheim]].  Some of the debug-tools are similar.

Support for AVR32 has been dropped from [[Linux]] as of kernel 4.12;<ref>{{cite web|url=https://github.com/torvalds/linux/commit/26202873bb51fafdaa51be3e8de7aab9beb49f70|title=avr32: remove support for AVR32 architecture|website=[[GitHub]]|access-date=2017-09-21}}</ref> Atmel has switched mostly to M variants of the [[ARM architecture]].

== Architecture ==
The AVR32 has at least two micro-architectures, the AVR32A and AVR32B.  These differ in the instruction set architecture, register configurations and the use of caches for instructions and data.<ref>{{cite web | url=http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf | title=AVR32 Architecture Document | publisher=[[Atmel]] | access-date=2008-06-15 | archive-date=2012-03-24 | archive-url=https://web.archive.org/web/20120324031215/http://www.atmel.com/Images/doc32000.pdf | url-status=dead }}</ref>

The '''AVR32A''' CPU cores are for inexpensive applications.  They do not provide dedicated hardware registers for shadowing the register file, status and return address in [[interrupt]]s. This saves chip area at the expense of slower interrupt-handling.

The '''AVR32B''' CPU cores are designed for fast interrupts.  They have dedicated registers to hold these values for interrupts, exceptions and supervisor calls. The AVR32B cores also support a [[Java virtual machine]] in hardware.<ref name="techref">{{cite web | url=http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf | title=AVR32 AP Technical Reference Manual | publisher=[[Atmel]] | access-date=2008-12-12| archive-url= https://web.archive.org/web/20081203013730/http://atmel.com/dyn/resources/prod_documents/doc32001.pdf| archive-date= 3 December 2008 | url-status= live}}</ref>

The AVR32 instruction set has [[16-bit]] (compact) and 32-bit (extended) instructions, similar to e.g. some ARM, with several specialized instructions not found in older ARMv5 or ARMv6 or [[MIPS architecture|MIPS32]]. Several U.S. patents are filed for the AVR32 ISA and design platform.

Just like the [[Atmel AVR|AVR 8-bit microcontroller]] architecture, the AVR32 was designed for high [[code density]] (packing much function in few instructions) and fast instructions with few clock cycles. Atmel used the independent benchmark consortium [[EEMBC]] to benchmark the architecture with various compilers and consistently outperformed both ARMv5 16-bit ([[ARM architecture#Thumb|Thumb]]) code and ARMv5 32-bit ([[ARM architecture|ARM]]) code by as much as 50% on code-size and 3× on performance.{{Citation needed|date=December 2009}}

Atmel says the "picoPower" AVR32 AT32UC3L consumes less than 0.48&nbsp;mW/MHz in active mode, which it claimed, at the time, used [[low-power electronics|less power]] than any other [[32-bit]] CPU.<ref>{{cite press release| url=http://www.atmel.com/dyn/products/view_detail.asp?FileName=AT32UC3L_6_22.html&family_id=682 |title = Proven, Innovative Microcontroller Technologies with Low Power and High Performance |quote=Atmel Introduces AVR32 Microcontroller which Lowers Industry's Best Power Consumption by 63%; picoPower AVR32 AT32UC3L Microcontroller offers less than 0.48&nbsp;mW/MHz Active and below 100 nA Sleep Mode}}</ref> Then in March 2015, Amtel claimed their new [[ARM Cortex-M0+|Cortex-M0+]]-based microcontrollers using [[ARM Holdings]]' [[ARM architecture]], not their own [[instruction set]], "has broken all ultra-low power performance barriers to date" by requiring only 35&nbsp;μA/MHz.<ref>
{{cite web
|url=http://blog.atmel.com/2015/03/30/sam-l-family-now-the-worlds-lowest-power-arm-cortex-m-based-solution/
|date=March 30, 2015
|quote=These Cortex-M0+-based MCUs can maintain system functionality, all while consuming just one-third the power of comparable products on the market today. This device delivers ultra-low power running down to 35μA/MHz in active mode, consuming less than 900nA with full 32[[kibibyte|kB]] RAM retention.[..]<br />"In Atmel's announcement last year for the company's SAM L21 family, I had pointed out the amazingly low current consumption ratings for both the active and sleep mode operation of this product family&nbsp;– now I can confirm this opinion with concrete data derived from the EEMBC ULPBench," explained Markus Levy, EEMBC President and Founder. "Atmel achieved the lowest power of any Cortex-M based processor and MCU in the world because of its patented ultra-low power picoPower technology. These ULPBench results are remarkable, demonstrating the company's low-power expertise utilizing DC-DC conversion for voltage monitoring, as well as other innovative techniques."<br />While running the EEMBC ULPBench, the SAM L21 achieves a staggering score of 185, the highest publicly-recorded score for any Cortex-M based processor or MCU in the world&nbsp;— and significantly higher than the 167 and 123 scores announced by other vendors. The SAM L21 family consumes less than 940nA with full 40[[kibibyte|kB]] SRAM retention, real-time clock and calendar and 200nA in the deepest sleep mode.
|access-date=27 April 2015
|title=SAM L family now the world's lowest power ARM Cortex-M based solution
|archive-url=https://archive.today/20150427221743/http://blog.atmel.com/2015/03/30/sam-l-family-now-the-worlds-lowest-power-arm-cortex-m-based-solution/
|archive-date=27 April 2015
|url-status=dead
|df=dmy-all
}}
</ref>

== Implementations ==
The AVR32 architecture was used only in Atmel's own products. In 2006, Atmel launched the AVR32A: The AVR32 AP7 core, a 7-stage [[Instruction pipeline|pipelined]], [[cache (computing)|cache]]-based design platform.<ref name="techref"/> This "AP7000" implements the AVR32B architecture, and supports a hardware [[floating-point unit|FPU]], [[SIMD]] (single instruction multiple data) [[Digital signal processor|DSP]] ([[digital signal processing]]) instructions to the [[RISC]] instruction-set, in addition to Java hardware acceleration.  It includes a Memory Management Unit (MMU) and supports operating systems like [[Linux]].  In early 2009, the rumored AP7200 follow-on processor was held back, with resources going into other chips.

In 2007, Atmel launched the second AVR32: The AVR32 UC3 core.  This is designed for microcontrollers, using on-chip flash memory for program storage and running without an MMU (memory management unit). The AVR32 UC3 core uses a three-stage [[Instruction pipeline|pipelined]] Harvard architecture specially designed to optimize instruction fetches from on-chip [[flash memory]].<ref>{{cite web|url=http://atmel.com/dyn/resources/prod_documents/doc32002.pdf |title=AVR32UC Technical Reference Manual |publisher=[[Atmel]] |access-date=2008-06-15 |url-status=dead |archive-url=https://web.archive.org/web/20090205015739/http://www.atmel.com/dyn/resources/prod_documents/doc32002.pdf |archive-date=2009-02-05 }}</ref> The AVR32 UC3 core implements the AVR32A architecture.  It shares the same instruction set architecture (ISA) as its AP7 sibling, but differs by not including the optional SIMD instructions or Java support.  The FPU instruction set is optional, and was not implemented in the initial families of UC3 microcontrollers. It shares more than 220 instructions with the AVR32B. The ISA features atomic bit manipulation to control on-chip peripherals and general purpose I/Os and fixed point [[Digital signal processor|DSP]] arithmetic.

Both implementations can be combined with a compatible set of peripheral controllers and buses first seen in the [[AT91SAM]] ARM-based platforms.  Some peripherals first seen in the AP7000, such as the high speed USB peripheral controller, and standalone DMA controller, appeared later in updated ARM9 platforms and then in the ARM Cortex-M3 based products.

Both AVR32 cores include a [[Nexus (standard)|Nexus]] class 2+ based On-Chip Debug framework build with [[JTAG]].

The UC3 C core, announced at the Electronica 2010 in Munich Germany on November 10, 2010, was the first member of the UC3 family to implement FPU support.<ref>{{cite web |url=http://www.atmel.com/dyn/products/view_detail.asp?FileName=Atmel_Introduces_First_32-bit_AVR_Microcontroller_UC3.html&family_id=607 |archive-url=https://web.archive.org/web/20101122050804/http://www.atmel.com/dyn/products/view_detail.asp?FileName=Atmel_Introduces_First_32-bit_AVR_Microcontroller_UC3.html&family_id=607 |archive-date=2010-11-22  | title=Atmel Introduces First 32-bit AVR Microcontroller Featuring Floating Point Unit | publisher=[[Atmel]] | access-date=2011-03-26}}</ref>

== Devices ==

=== AP7 core ===
On April 10, 2012 Atmel announced the End of Life of AP7 Core devices from April 4, 2013.<ref>{{Cite web|url=http://www.atmel.com/About/Quality/obsolescence/obsolete_items.aspx?searchText=ap7|title = Smart &#124; Connected &#124; Secure &#124; Microchip Technology}}</ref>
*[https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32AP7000]
*[http://www.atmel.com/dyn/products/product_card.asp?part_id=4084 AT32AP7001]
*[http://www.atmel.com/dyn/products/product_card.asp?part_id=4085 AT32AP7002]

=== UC3 core ===
If the devicename ends in *AU this is an Audio version, these allow the execution of Atmel licensed Audio firmware IPs.

If the devicename ends in *S it includes an AES Crypto Module.
;A0/A1 Series{{snd}} ''devices deliver 91 [[Dhrystone]] MIPS (DMIPS) at 66&nbsp;MHz (1 flash wait-state) and consume 40 mA @66&nbsp;MHz at 3.3&nbsp;V.''
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3A0128]
* [http://www.atmel.com/devices/AT32UC3A0128AU.aspx AT32UC3A0128AU]
* [http://www.atmel.com/devices/AT32UC3A0256.aspx AT32UC3A0256]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3A0256AU]
* [http://www.atmel.com/devices/AT32UC3A0512.aspx AT32UC3A0512]
* [http://www.atmel.com/devices/AT32UC3A0512AU.aspx AT32UC3A0512AU]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3A1128]
* [http://www.atmel.com/devices/AT32UC3A1256AU.aspx AT32UC3A1256AU]
* [http://www.atmel.com/devices/AT32UC3A1512.aspx AT32UC3A1512]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3A1512AU]

;A3/A4 Series{{snd}} ''devices deliver 91 [[Dhrystone]] MIPS (DMIPS) at 66&nbsp;MHz and consume 40&nbsp;mA @66&nbsp;MHz at 3.3&nbsp;V.''
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3A364]
* [http://www.atmel.com/devices/AT32UC3A364S.aspx AT32UC3A364S]
* [http://www.atmel.com/devices/AT32UC3A3128.aspx AT32UC3A3128]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3A3128S]
* [http://www.atmel.com/devices/AT32UC3A3256.aspx AT32UC3A3256]
* [http://www.atmel.com/devices/AT32UC3A3256AU.aspx AT32UC3A3256AU]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3A3256S]
* [http://www.atmel.com/devices/AT32UC3A464.aspx AT32UC3A464]
* [http://www.atmel.com/devices/AT32UC3A464S.aspx AT32UC3A464S]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3A4128]
* [http://www.atmel.com/devices/AT32UC3A4128S.aspx AT32UC3A4128S]
* [http://www.atmel.com/devices/AT32UC3A4256.aspx AT32UCA4256]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3A4256S]

;B Series{{snd}} ''deliver 72 Dhrystone MIPS (DMIPS) at 60&nbsp;MHz and consume 23&nbsp;mA @66&nbsp;MHz at 3.3V.''
* [http://www.atmel.com/devices/AT32UC3B064.aspx AT32UC3B064]
* [http://www.atmel.com/devices/AT32UC3B0128.aspx AT32UC3B0128]
* [http://www.atmel.com/devices/AT32UC3B0128AU.aspx AT32UC3B0128AU]
* [http://www.atmel.com/devices/AT32UC3B0256.aspx AT32UC3B0256]
* [http://www.atmel.com/devices/AT32UC3B0512.aspx AT32UC3B0512]
* [http://www.atmel.com/devices/AT32UC3B0512AU.aspx AT32UC3B0512AU]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3B164]
* [http://www.atmel.com/devices/AT32UC3B1128.aspx AT32UC3B1128]
* [http://www.atmel.com/devices/AT32UC3B1256.aspx AT32UC3B1256]
*[https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3B1512]

;C Series{{snd}} ''devices deliver 91 [[Dhrystone]] MIPS (DMIPS) at 66&nbsp;MHz and consume 40&nbsp;mA @66&nbsp;MHz at 3.3&nbsp;V.''
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3C064C]
* [http://www.atmel.com/devices/AT32UC3C0128C.aspx AT32UC3C0128C]
* [http://www.atmel.com/devices/AT32UC3C0256C.aspx AT32UC3C0256C]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3C0512C]
* [http://www.atmel.com/devices/AT32UC3C0512CAU.aspx AT32UC3C0512CAU]
* [http://www.atmel.com/devices/AT32UC3C164C.aspx AT32UC3C164C]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3C1128C]
* [http://www.atmel.com/devices/AT32UC3C1256C.aspx AT32UC3C1256C]
* [http://www.atmel.com/devices/AT32UC3C1512C.aspx AT32UC3C1512C]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3C264C]
* [http://www.atmel.com/devices/AT32UC3C2128C.aspx AT32UC3C2128C]
* [http://www.atmel.com/devices/AT32UC3C2256C.aspx AT32UC3C2256C]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3C2512C]
'''D Series{{snd}} ''The low-power UC3D embeds [[Atmel SleepWalking|SleepWalking]] technology that allows a peripheral to wake the device from sleep mode.'''''
*  [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view ATUC64D3]
*  [http://www.atmel.com/devices/ATUC128D3.aspx ATUC128D3]
*  [http://www.atmel.com/devices/ATUC64D4.aspx ATUC64D4]
*  [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view ATUC128D4]
;L Series{{snd}} ''deliver 64 Dhrystone MIPS (DMIPS) at 50&nbsp;MHz and consume 15&nbsp;mA @50&nbsp;MHz at 1.8&nbsp;V.''
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3L016]
* [http://www.atmel.com/devices/AT32UC3L032.aspx AT32UC3L032]
* [http://www.atmel.com/devices/AT32UC3L064.aspx AT32UC3L064]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3L0128]
* [http://www.atmel.com/devices/AT32UC3L0256.aspx AT32UC3L0256]
* [http://www.atmel.com/devices/ATUC64L3U.aspx ATUC64L3U]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view ATUC128L3U]
* [http://www.atmel.com/devices/ATUC256L3U.aspx ATUC256L3U]
* [http://www.atmel.com/devices/ATUC64L4U.aspx ATUC64L4U]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view ATUC128L4U]
* [http://www.atmel.com/devices/ATUC256L4U.aspx ATUC256L4U]

== Boards ==
[[File:Atmel EVK1100 Development Board (8042276987).jpg|thumb|Atmel EVK1100 Development Board]]
* [http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918 AT32AP7000 development environment (STK1000)]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32AP7000 Network Gateway Kit (NGW100)]
* [https://web.archive.org/web/20101110075256/http://www.hammerhead.ch/ AT32AP7000 board with FPGA, video decoder and Power over Ethernet (Hammerhead)]
* [https://web.archive.org/web/20070228011808/http://www.indefia.com/products/hardware/emblinux/ AT32AP7000 Indefia Embedded Linux Board with ZigBee support]
* [http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4254 All AT32UC3 Series Generic Evaluation platform (STK600)]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3A0/1 Series Evaluation Kit (EVK1100)]
* [http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4428 AT32UC3A0/1 Series Audio Evaluation Kit (EVK1105)]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3A3 Series Evaluation Kit (EVK1104)]
* [http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4175 AT32UC3B Series Evaluation Kit (EVK1101)]
* [https://web.archive.org/web/20091122203153/http://store.stackfoundry.com/copper-avr32-stick.html AT32UC3B Breadboard module (Copper)]
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view AT32UC3A1 Breakout/Small Development board (Aery32)]

== See also ==
* [[Atmel]]
* [[Atmel AVR]]
* [[Arduino]]

== References ==
{{reflist}}

== External links ==
{{Commons category}}
* [https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view Atmel AVR32]* {{Cite web |url=http://avr32linux.org/twiki/bin/view |title=AVR32 Linux Project |access-date=May 9, 2013 |archive-url=https://web.archive.org/web/20110902093741/http://avr32linux.org/twiki/bin/view |archive-date=September 2, 2011 |url-status=dead |df=mdy-all }} (now dead) contained recent Linux kernel patches and [[GNU Compiler Collection|GCC]] / [[binutils]] and so on.

{{RISC-based processor architectures}}

[[Category:Atmel microcontrollers]]
[[Category:Instruction set architectures]]