View source for AMD 10h

{{short description|Microprocessor microarchitecture by AMD}}
{{Cleanup|reason=The page needs cleanup after the release of Phenom II X6.|date=September 2024}}
{{Infobox CPU
| name           = K10 / Family 10h
| image          = 
| image_size     = 138px
| caption        = 
| produced-start = 2007
| produced-end   = 2012
| slowest        = 1700
| slow-unit      = MHz
| fastest        = 3700
| fast-unit      = MHz
| fsb-slowest    = 1000
| fsb-slow-unit  = MHz
| fsb-fastest    = 2000
| fsb-fast-unit  = MHz
| size-from      = [[65 nanometer|65 nm]]
| size-to        = [[32 nanometer|32 nm]]
| manuf1         = [[AMD]]
| core1          = [[Sempron]]
| core2          = [[Sempron|Sempron X2]]
| core3          = [[Athlon 64 X2#Kuma (65 nm SOI)|Athlon X2]]
| core4          = [[Athlon II]]
| core5          = [[Opteron]]
| core6          = [[AMD Phenom|Phenom]]
| core7          = [[Phenom II]]
| core8          = [[AMD Turion#Turion II|Turion II]]
| core9          = [[AMD Accelerated Processing Unit#K10 architecture (2011): Llano|AMD APU]]
| predecessor    = [[AMD K8|K8 - Hammer]]
| successor      = [[Bulldozer (microarchitecture)|Bulldozer - Family 15h]]
| sock1          = [[Socket AM2]]
| sock2          = [[Socket AM2+]]
| sock3          = [[Socket AM3]]
| sock4          = [[Socket F]]
| sock5          = Socket ASB2
| sock6          = [[Socket C32]]
| sock7          = [[Socket G34]]
| sock8          = [[Socket FM1]]
| sock9          = [[Socket FS1]]
| arch           = [[X86-64#AMD64|AMD64]] ([[X86-64#Microarchitecture levels|x86-64-v1]])

| support status = iGPU unsupported

}}

The '''AMD Family 10h''', or '''K10''', is a [[microprocessor]] [[microarchitecture]] by [[Advanced Micro Devices|AMD]] based on the K8 microarchitecture.<ref name=leon>{{cite web|title=List of AMD CPU microarchitectures - LeonStudio|url=http://leonstudio.org/p/165|website=LeonStudio - CodeFun|access-date=12 September 2015|date=3 August 2014|archive-date=26 September 2020|archive-url=https://web.archive.org/web/20200926092938/http://leonstudio.org/p/165|url-status=dead}}</ref> The first [[Opteron#Micro-architecture update|third-generation Opteron]] products for servers were launched on September 10, 2007, with the [[Phenom (processor)|Phenom]] processors for desktops following and launching on November 11, 2007, as the immediate successors to the K8 series of processors ([[Athlon 64]], [[Opteron]], 64-bit [[Sempron]]).

==Nomenclature==
It appears that AMD has not used K-nomenclature (which originally stood for "Kryptonite" in the [[AMD K5|K5 processor]]<ref name="Forbes-Chip-Names">{{cite news | first=Arik | last=Hesseldahl | title=Why Cool Chip Code Names Die | date=2000-07-06 | url =https://www.forbes.com/2000/07/06/mu2.html | work =forbes.com | access-date = 2007-07-14 }}</ref>) from the time after the use of the codename ''K8'' for the [[AMD K8]] or [[Athlon 64]] processor family, since no K-nomenclature naming convention beyond K8 has appeared in official AMD documents and press releases after the beginning of 2005.

The name "''K8L''" was first coined by Charlie Demerjian in 2005, at the time a writer at ''[[The Inquirer]]'',<ref>{{cite web |url=http://www.theinquirer.net/default.aspx?article=27421 |title=The Inquirer report |work= [[The Inquirer]] |author= |date= |archive-url=https://web.archive.org/web/20070906163444/http://www.theinquirer.net/default.aspx?article=27421 |archive-date=September 6, 2007 |url-status=unfit}}</ref> and was used by the wider IT community as a convenient shorthand<ref name="Inquirer1">{{cite news|last=Valich |first=Theo |title=AMD explains K8L misnomer |url=http://www.theinquirer.net/default.aspx?article=37444 |publisher=The Inquirer |access-date=2007-03-16 |archive-url=https://web.archive.org/web/20070210133934/http://www.theinquirer.net/default.aspx?article=37444 |archive-date=February 10, 2007 |url-status=unfit }}</ref> while according to AMD official documents, the processor family was termed "AMD Next Generation Processor Technology".<ref>[https://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_543~111541,00.html Official Announcement of "AMD Next Generation Processor Technology"]</ref>

The microarchitecture has also been referred to as ''Stars'', as the codenames for desktop line of processors was named under stars or constellations (the initial Phenom models being codenamed Agena and [[Toliman]]).

In a video interview,<ref>[http://www.syndrome-oc.net/articles.php?article=94&lang=en Video interview of Giuseppe Amato (AMD's Technical Director, Sales and Marketing EMEA)] {{webarchive|url=https://archive.today/20090712021634/http://www.syndrome-oc.net/articles.php?article=94&lang=en |date=2009-07-12 }} in February 2007</ref> Giuseppe Amato confirmed that the codename is '''K10'''.

It was revealed, by ''The Inquirer'' itself, that the codename "''K8L''" referred to a low-power version of the K8 family, later named [[Turion 64]], and that '''K10''' was the official codename for the microarchitecture.<ref name="Inquirer1" />

AMD refers to it as '''Family 10h Processors''', as it is the successor of the Family 0Fh Processors (codename K8). 10h and 0Fh refer to the main result of the [[CPUID]] [[x86]] processor instruction. In [[hexadecimal]] numbering, 0Fh (h represents hexadecimal numbering) equals the [[decimal]] number 15, and 10h equals decimal 16. (The "K10h" form that sometimes pops up is an improper hybrid of the "K" code and Family identifier number.)

==Schedule of launch and delivery==

===Timeline===

====Historical information====
<!-- Much of this fell foul of [[WP:CRYSTAL]] even when it was current, and today it's of very little interest. -->
In 2003, AMD outlined the features for upcoming generations of microprocessors after the K8 family of processors in various events and analyst meetings, including the Microprocessor Forum 2003.<ref>[http://pc.watch.impress.co.jp/docs/2006/0119/kaigai233_01l.gif Microprocessor Forum 2003 presentation slide]</ref> The outlined features to be deployed by the next-generation microprocessors are as follows:
* [[thread (computing)|Threaded]] architectures.
* Chip level [[multiprocessing]].
* Huge scale MP (multi-processor) machines.
* 10&nbsp;GHz operation.
* Much higher performance [[superscalar]], [[out-of-order execution|out-of-order]] CPU core.
* Huge caches.
* Media/[[vector processing]] extensions.
* Branch and memory hints.
* Security and [[Hardware-assisted virtualization|virtualization]].
* Enhanced Branch Predictors.
* Static and dynamic power management.
<!--
On April 13, 2006, Henri Richard, AMD executive vice president and chief officer for marketing and sales, acknowledged<ref>{{cite web |last=Hall |first=Chris |title=Re-defining microprocessors: Q&A with AMD's Henri Richard |url=http://www.digitimes.com/bits_chips/a20060313PR201.html |publisher=DigiTimes.com |access-date=2007-03-18| archive-url= https://web.archive.org/web/20060313163633/http://www.digitimes.com/bits_chips/a20060313PR201.html| archive-date=March 13, 2006| url-status= live}}</ref> the existence of the new microarchitecture in an interview.-->

In June 2006, AMD executive vice president Henri Richard had an interview with ''DigiTimes'' commented on the upcoming processor developments:

{{blockquote|
Q: What is your broad perspective on the development of AMD processor technology over the next three to four years?

A: Well, as Dirk Meyer commented at our analysts meeting, we're not standing still. We've talked about the refresh of the current K8 architecture that will come in '07, with significant improvements in many different areas of the processor, including integer performance, floating point performance, memory bandwidth, interconnections and so on.|AMD Executive Vice President, Henri Richard|Source: DigiTimes Interview with Henri Richard<ref>[http://www.digitimes.com/news/a20060628VL201.html AMD's vision for next few years] - an interview with Henri Richard</ref>}}

<!-- Entire section was [[WP:CRYSTAL]] in 2006 and is of no interest in 2023
====Confirmation of time frames====
[[File:Barcelona die.jpg|thumb|right|"Barcelona" die shot]]

On July 21, 2006, AMD President and Chief operating officer (COO) Dirk Meyer and Senior VP Marty Seyer confirmed that the launch date of new [[microprocessor]]s of ''Revision H'' under the new microarchitecture is slated for the middle of 2007; and that it will contain a [[Multi-core|quad core]] version for [[server (computing)|servers]], [[workstations]], and high-end [[desktop computer|desktops]], as well as a dual core version for consumer Desktops. Some of the ''Revision H'' Opterons shipped in 2007 will have a [[thermal design power]] of 68 [[Watt|W]].

On August 15, 2006, at the launch of the first [[Socket F]] dual-core [[Opteron]]s, AMD announced that the firm had reached the final design stage ([[tape-out]]) of quad-core [[Opteron]] parts. The next stages are testing and validation, with sampling to follow after several months.<ref>{{cite news | url=http://www.crn.com/sections/breakingnews/dailyarchives.jhtml?articleId=191902502 | title=Next-Generation AMD Opteron Paves The Way For Quad-Core | publisher=crn.com | date=2006-08-15 | access-date=2007-04-19 | archive-url=https://web.archive.org/web/20120206213118/http://www.crn.com/sections/breakingnews/dailyarchives.jhtml?articleId=191902502 | archive-date=2012-02-06 | url-status=dead }}</ref>

On June 29, 2007, AMD stated that server processors codenamed ''Barcelona'' will ship in August 2007, and corresponding server systems from partners will ship in September of the same year.<ref>{{cite news | url=https://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_543~118193,00.html | title=AMD to Ship Industry's First Native x86 Quad-Core Processors In August | publisher=AMD | date=2007-06-29}}</ref>

On August 13, the reported ship dates for the first Barcelona processors were set for September 10, 2007. They announced the Opteron 2348 and 2350 will have core frequencies of 1.9&nbsp;GHz and 2.0&nbsp;GHz.<ref>{{cite news | url=http://www.tgdaily.com/content/view/33338/139/ | archive-url=https://web.archive.org/web/20071016184512/http://tgdaily.com/content/view/33338/139/ | url-status=dead | archive-date=2007-10-16 | title=AMD to launch two Barcelona-based processors in September | publisher=tgdaily.com | date=2007-08-13 }}</ref> --><!--

====Internal codenames====
As of November 2006, reports leaked the upcoming desktop part codenames ''Agena'', ''Agena FX'', and the core speeds of the parts range from 2.4&nbsp;GHz - 2.9&nbsp;GHz respectively, 512&nbsp;[[Kibibyte|KB]] L2 [[CPU cache|cache]] each core, 2&nbsp;[[Mebibyte|MB]] L3 cache, using HyperTransport 3.0, with a TDP of 125 W.<ref>{{cite news|url=http://www.hkepc.com/bbs/itnews.php?tid=678736 |archive-url=https://web.archive.org/web/20061031195830/http://www.hkepc.com/bbs/itnews.php?tid=678736 |url-status=dead |archive-date=2006-10-31 |title=AMD Quad-Core Altair upcoming in 2007 Q3 |publisher=HKEPC |date=2006-10-03 }}</ref> In recent reports, single core variants (codenamed ''Spica'') and dual core with or without L3 cache (codenamed ''Kuma'' and ''Rana'' respectively) are available under the same microarchitecture.<ref>{{cite news|url=http://www.hkepc.com/bbs/itnews.php?tid=679375 |archive-url=https://web.archive.org/web/20061011233437/http://www.hkepc.com/bbs/itnews.php?tid=679375 |url-status=dead |archive-date=2006-10-11 |title=AMD to enter K10 era in 2H 2007 |publisher=HKEPC |date=2006-10-04 }}</ref>

During the AMD Analyst Day 2006 on December 14, 2006, AMD announced their official timeline for server, desktop and mobile processors.<ref name="AMD-Dec1">{{cite news | url=http://www.cdrinfo.com/sections/news/Details.aspx?NewsId=19298 | title=2006 Analyst Day Slides | access-date=2008-12-02 | archive-url=https://web.archive.org/web/20140221220721/http://www.cdrinfo.com/sections/news/Details.aspx?NewsId=19298 | archive-date=2014-02-21 | url-status=dead }}</ref> For the servers segment, AMD will unveil two new processors based on the architecture codenamed "''Barcelona''" and "''Budapest''" for 8/4/2-way and 1-way servers respectively. For the second half of 2007, [[HyperTransport]] 3.0 and [[Socket AM2+]] will be unveiled, which are designed for the specific implementation of the aforementioned consumer quad core desktop chip series, with naming convention changes from city names (up to middle of 2007) to stars or constellations after that, such as ''Agena''; in addition, the [[AMD Quad FX platform]] and its immediate successor will support the high end enthusiast dual-processor versions of the chip, codenamed as ''Agena FX'', updates the processors line for [[AMD Quad FX platform]]. As with the server chips codenamed ''Barcelona'', the new desktop quad core series will feature a shared L3 cache, 128-bit floating point (FP) units and an enhanced microarchitecture. ''Agena'' will be the native quad-core processor for the desktop. ''Kuma'', a dual-core variant will follow on in Q3 while ''Rana'', the dual-core version with no shared L3 cache is expected at the end of the year.

====Subsequent product launches====
More information about the upcoming chip codenamed "''Montreal''" on the server roadmap<ref>{{cite web |url=http://theinquirer.net/default.aspx?article=38634 |title=The Inquirer report |work=[[The Inquirer]] |author= |date= |archive-url=https://web.archive.org/web/20070912205924/http://theinquirer.net/default.aspx?article=38634 |archive-date=2007-09-12 |url-status=unfit}}</ref> using [[Multi-chip module|MCM]] technique of two "''Shanghai''" cores with a total of 12&nbsp;MB L3 cache<ref>[http://www.fudzilla.com/index.php?option=com_content&task=view&id=529&Itemid=1 FudZilla report]</ref> codenamed [[AMD K10.5]].<ref>[http://www.fudzilla.com/index.php?option=com_content&task=view&id=496&Itemid=35 FudZilla report]</ref> The desktop variant for ''Shanghai'' is codenamed ''Ridgeback''.<ref>[http://www.fudzilla.com/index.php?option=com_content&task=view&id=2214&Itemid=1 Fudzilla report], retrieved August 1, 2007 {{webarchive |url=https://web.archive.org/web/20071016182633/http://fudzilla.com/index.php?option=com_content&task=view&id=2214&Itemid=1 |date=October 16, 2007 }}</ref> Afterwards is the release of products based on the ''[[Bulldozer (processor)|Bulldozer]]'' cores, which is optimized with integrated graphics core ([[AMD Accelerated Processing Unit]]) or native octal-core (8 core) server architecture (codenamed ''Sandtiger''), and the ''[[Bobcat (processor)|Bobcat]]'' core, optimized for low-power operations.

====Change of model nomenclatures====
During Computex 2007 in early June, new information regarding the naming schemes of upcoming AMD microprocessors emerged. Additional letters indicating both performance and power envelope will precede the 4 digit model number.<ref>{{cite news | url=http://blog.wired.com/gadgets/2007/06/how_to_decipher.html | archive-url=https://web.archive.org/web/20070606085324/http://blog.wired.com/gadgets/2007/06/how_to_decipher.html | url-status=dead | archive-date=June 6, 2007 | title=How to decipher AMD's new CPU naming code | publisher=Gadget Lab | date=2007-06-04 }}</ref>

The model numbers of the new line of processors were apparently changed from the [[PR rating]]s used by its predecessors, the [[AMD K8|Athlon 64]] series processors (except [[AMD Phenom FX|Phenom FX]] series, being suggested to follow the nomenclature of [[Athlon 64 FX]] series). As reported by DailyTech,<ref name="dailytech7537">{{Cite web |url=http://dailytech.com/AMD+Expands+Upcoming+Processor+Branding/article7537.htm |title=DailyTech report |access-date=2007-06-05 |archive-url=https://web.archive.org/web/20071014020053/http://www.dailytech.com/AMD+Expands+Upcoming+Processor+Branding/article7537.htm |archive-date=2007-10-14 |url-status=dead }}</ref> the model numbers are in alpha-numeric format as AA-@### where AA are alphabetical letters, the first letter indicating the processor class and the second indicating the typical [[thermal design power|TDP]] power envelope. The character @ is the series indicator, which varies by branding (see below table), and the last three characters (###) are the model number, with higher numbers indicating greater performance.

Not much information was known about the details of the model numbers, but the processors will be divided into three segments: Premium, Intermediate, and Value. Premium segment model numbers have processor class "G", Intermediate segment "B", and Value level "L", as discovered on the web from the AsRock website.<ref>[http://xtreview.com/images/athlon-X2-BE-235001-3.gif XTReview image: AsRock BIOS 1.40 support Athlon X2 BE-xxxx and Sempron LE-xxxx processors]</ref> Similarly, three levels of TDP, "more than 65W", "65W", and "less than 65W", are indicated by the letters "P", "S", and "E" respectively.<ref name="dailytech7537"/>

As of November 2007, AMD has removed the letters from the model names and X2/X3/X4 monikers for depicting the number of cores of the processor, leaving just a four digit model number with the first character being the sole identification of the processor family,<ref name="vrzone-0710">{{cite web|url=http://www.vr-zone.com/articles/AMD_Revised_Desktop_Model_Number_Structure/5330.html |title=AMD Revised Desktop Model Number Structure |publisher=VR-Zone |date=2007-10-09 |url-status=dead |archive-url=https://web.archive.org/web/20071011194645/http://www.vr-zone.com/articles/AMD_Revised_Desktop_Model_Number_Structure/5330.html |archive-date=October 11, 2007 }}</ref> while Sempron remained using the LE prefix, as follows:

{|class="wikitable" style="margin:1em auto; width:45%;"
|+Series number<ref>[http://www.vr-zone.com/articles/AMD_Revised_Desktop_Model_Number_Structure/5330.html VR-Zone report], retrieved October 9, 2007 {{webarchive |url=https://web.archive.org/web/20071011194645/http://www.vr-zone.com/articles/AMD_Revised_Desktop_Model_Number_Structure/5330.html |date=October 11, 2007 }}</ref>
!  style="text-align:center; width:60%;"| Processor series !! style="text-align:center;"| Indicator
|- style="text-align:center;" 
||Phenom quad-core (''Agena'') || style="text-align:center;"|'''9'''
|- style="text-align:center;" 
||Phenom triple-core (''Toliman'') || style="text-align:center;"|'''8'''
|- style="text-align:center;" 
||Athlon dual-core (''Kuma'') || style="text-align:center;"|'''7'''
|- style="text-align:center;" 
||Athlon single-core (''Lima'') || style="text-align:center;"|'''1'''
|- style="text-align:center;" 
||Sempron LE single-core (''Sparta'') || style="text-align:center;"|'''1'''
|}-->

===Live demonstrations===
On November 30, 2006, AMD live demonstrated the native quad core chip known as "Barcelona" for the first time in public,<ref>{{cite news | url=http://news.cnet.com/2061-10791_3-6139758.html | title=AMD Demonstrates Its Quad Core Server Chips | publisher=CNET.com | date=2006-11-30}}</ref> while running Windows Server 2003 64-bit Edition. AMD claims 70% scaling of performance in real world loads, and better performance than [[Intel]] [[Xeon]] 5355 processor codenamed ''Clovertown''.<ref>{{cite news | url=http://www.legitreviews.com/article/426/1/ | title=AMD Demonstrates Barcelona; The First True, Native Quad Core Opteron | publisher=legitreviews.com | date=2006-11-30}}</ref><!-- More details regarding this first revision of the next generation AMD microprocessor architecture surfaced  including their clock speeds.<ref>{{cite news | url=https://arstechnica.com/news.ars/post/20061206-8363.html | title=Quick Look at AMD Quad Core Barcelona | publisher=arstechnica.com | date=6 December 2006}}</ref><ref>{{cite web |url=http://theinquirer.net/default.aspx?article=36195 |title=The Inquirer article |work=[[The Inquirer]] |author= |date= |archive-url=https://web.archive.org/web/20070516002734/http://theinquirer.net/default.aspx?article=36195 |archive-date=May 16, 2007 |url-status=unfit}}</ref>-->

On January 24, 2007, AMD Executive Vice President Randy Allen claimed that in live tests, in regard to a wide variety of workloads, "Barcelona" was able to demonstrate 40% performance advantage over the comparable Intel Xeon codenamed ''[[Clovertown (microprocessor)|Clovertown]]'' dual-processor (2P) quad-core processors.<ref>{{cite news | url=http://www.dailytech.com/article.aspx?newsid=5863 | title=AMD Expects Quad Core Barcelona to Outperform Clovertown by 40% | publisher=dailytech.com | date=2007-01-25 | access-date=2007-04-19 | archive-url=https://web.archive.org/web/20070227223316/http://www.dailytech.com/Article.aspx?newsid=5863 | archive-date=2007-02-27 | url-status=dead }}</ref> The expected performance of [[floating point]] per core would be approximately 1.8 times that of the K8 family, at the same clock speed.<ref>{{cite news | title=Go to 'Barcelona' over 'Cloverton' | url=http://news.cnet.com/AMD+Go+to+Barcelona+over+Clovertown+-+page+2/2100-1006_3-6152645-2.html?tag=st.num | publisher=CNET.com | date=2007-01-23}}</ref>

On May 10, 2007, AMD held a private event demonstrating the upcoming processors codenamed ''Agena FX'' and chipsets, with one demonstrated system being [[AMD Quad FX platform]] with one [[Radeon R600|Radeon HD 2900 XT]] [[video card|graphics card]] on the upcoming [[RD700 chipset series|RD790]] chipset. The system was also demonstrated real-time converting a [[720p]] video clip into another undisclosed format while all 8 cores were maxed at 100% by other tasks.<ref>{{Cite web |url=http://www.tgdaily.com/index.php?option=com_content&task=view&id=31977 |title=TGDaily report |access-date=2007-05-11 |archive-url=https://web.archive.org/web/20070926232509/http://www.tgdaily.com/index.php?option=com_content&task=view&id=31977 |archive-date=2007-09-26 |url-status=dead }}</ref>

===Sister microarchitecture===
<!-- The following needs to be rewritten in a way that isn't speculation
Also due in a similar time frame will be a sister [[microarchitecture]], which will focus on lower power consumption chips in mobile platforms as well as [[small form factor (desktop and motherboard)|small form factor]] features. This microarchitecture will contain specialized features such as mobile optimized [[crossbar switch]] and [[memory controller]] and other on-[[Integrated circuit|die]] components; link power management for [[HyperTransport]] 3.0; and others. At that time, AMD simply dubbed it "New Mobile Core", without giving a specific [[codename]].
-->
On the December 2006 analyst day, Executive vice president Marty Seyer announced a new mobile core codenamed ''[[Griffin (processor)|Griffin]]'' launched in 2008 with inherited power optimizations technologies from the K10 microarchitecture, but based on a K8 design.

====TLB bug====
In November 2007 AMD stopped delivery of Barcelona processors after a [[Software bug|bug]] in the [[translation lookaside buffer]] (TLB) of [[Stepping (version numbers)|stepping]] B2 was discovered that could rarely lead to a [[race condition]] and thus a system lockup.<ref>[http://www.dailytech.com/Understanding++AMDs+TLB+Processor+Bug/article9915.htm "Understanding AMD's TLB Processor Bug"]. ''Daily Tech''. {{Webarchive|url=https://web.archive.org/web/20090218235415/http://www.dailytech.com/Understanding++AMDs+TLB+Processor+Bug/article9915.htm |date=2009-02-18 }}. December 5, 2007</ref> A patch in [[BIOS]] or software worked around the bug by disabling cache for page tables, but it was connected to a 5 to 20% performance penalty. Kernel [[Patch (computing)|patches]] that would almost completely avoid this penalty were published for [[Linux]]. In April 2008, the new stepping B3 was brought to the market by AMD, including a fix for the bug plus other minor enhancements.<ref>[http://www.xbitlabs.com/articles/cpu/display/phenom-x4-9850.html "TLB Bug – in the Past"]. ''Xbit Labs''. {{webarchive|url=https://web.archive.org/web/20090209171447/http://xbitlabs.com/articles/cpu/display/phenom-x4-9850.html |date=2009-02-09 }}. March 26, 2008</ref>

==Features==

===Fabrication technology===

AMD has introduced the microprocessors manufactured at [[65 nm]] feature width using [[Silicon on insulator|Silicon-on-insulator (SOI)]] technology, since the release of K10 coincides with the volume ramp of this manufacturing process.<ref>{{cite news | url=http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2734 | title=An AMD Update: Fab 36 Begins Shipments, Planning for 65 nm process and AM2 Performance | publisher=AnandTech |date=2006-04-04}}</ref><!-- The servers will be produced for [[Socket F(1207)]] or later 1207-pin socket infrastructure, the only server socket on AMD's near-term roadmap; the desktop parts will come on [[Socket AM2]] or [[Socket AM2+]].--><!--

--><!--AMD announced during the Technology Analyst Day<ref>[https://www.amd.com/us-en/Corporate/InvestorRelations/0,,51_306_14047,00.html 2006 AMD Analyst Day 2006 page]  {{webarchive|url=https://web.archive.org/web/20090517005803/http://www.amd.com/us-en/Corporate/InvestorRelations/0%2C%2C51_306_14047%2C00.html |date=May 17, 2009 }}</ref> that the use of Continuous Transistor Improvement (CTI) and Shared Transistor Technology (STT) would finally lead to the implementation of [[Silicon-Germanium-On-Insulator]] (SGoI) on [[65 nm]] process CPUs.<ref>{{cite web |last=Ostrander |first=Daryl |title=2006 Technology Analyst Day Slides |url=https://www.amd.com/us-en/assets/content_type/DownloadableAssets/DarylOstranderAMDAnalystDay.pdf |publisher=Advanced Micro Devices |access-date=2007-03-19|archive-url = https://web.archive.org/web/20070113074105/http://www.amd.com/us-en/assets/content_type/DownloadableAssets/DarylOstranderAMDAnalystDay.pdf |archive-date = January 13, 2007}}</ref>

--><!-- Admissible as historical fact, but needs preceding "65nm" stuff to also be presented as historical fact rather than speculation: Later processors were manufactured using 45&nbsp;nm SOI technology.

"APU" K10 processors were manufactured using 32&nbsp;nm SOI technology.

Starting at 45&nbsp;nm, immersion lithography was used.-->

===Supported DRAM standards===
The [[AMD K8|K8]] family was known to be particularly sensitive to memory latency since its design gains performance by minimizing this through the use of an on-die [[memory controller]] (integrated into the CPU); increased latency in the external modules negates the usefulness of the feature. [[DDR2 SDRAM|DDR2 RAM]] introduces some additional latency over [[DDR SDRAM|DDR RAM]] since the [[Dynamic random access memory|DRAM]] is internally driven by a clock at one quarter of the external data frequency, as opposed to one half that of DDR. However, since the command clock rate in DDR2 is doubled relative to DDR and other latency-reducing features (e.g. additive latency) have been introduced, common comparisons based on [[CAS latency]] alone are not sufficient. For example, [[Socket AM2]] processors are known to demonstrate similar performance using DDR2 SDRAM as [[Socket 939]] processors that utilize DDR-400 SDRAM. K10 processors support [[DDR2 SDRAM]] rated up to DDR2-1066 (1066&nbsp;MHz).<ref>{{cite news |title=AMD's next-generation Star supports DDR2-1066 & SSE4a |url=http://www.techtalkz.com/processors-motherboards/4475-amd-s-next-generation-star-supports-ddr2-1066-sse4a.html |publisher=HKEPC Hardware |access-date=2007-03-19}}</ref>

While some desktop K10 processors are AM2+ supporting only DDR2, an AM3 K10 processor supports both DDR2 and DDR3. A few AM3 motherboards have both DDR2 and DDR3 slots (this does not mean that both types can be fitted at the same time), but for the most part they have only DDR3.

Lynx desktop processors only support DDR3, as they use the FM1 socket.<!--

===Higher computational throughput===
It was also reported by several sources (such as [[AnandTech]], [[The Inquirer]] and Geek.com) that the microprocessors implementing the microarchitecture will feature a doubling in the width of [[Streaming SIMD Extensions|SSE]] execution units in the cores. With the help of major improvements in the memory subsystem (such as load re-ordering and improved prefetch mechanisms) as well as the doubled [[Central processing unit#CPU Operation|instruction fetch]] and load, it is expected to increase the suitability of the processor to scientific and high-performance computing tasks and potentially improve its competitiveness with [[Intel]]'s [[Xeon]], [[Intel Core 2|Core 2]], [[Itanium 2]] and other contemporary microprocessors.

Many of the improvements in computational [[throughput]] of each core are listed below.-->

== Microarchitecture characteristics ==
[[Image:AMD K10 Arch.svg|right|thumb|upright=1.8|K10 architecture]]
[[Image:K10h.jpg|right|thumb|upright=0.75|K10 single core with overlay description, excluding the L2 cache array]]

Characteristics of the microarchitecture include the following:<ref>{{cite news |last=Shimpi |first=Anand Lal |url=http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2939 |title=Barcelona Architecture: AMD on the Counterattack |publisher=AnandTech |access-date=2007-03-18| archive-url= https://web.archive.org/web/20070319234707/http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2939| archive-date= 19 March 2007 | url-status= live}}</ref>

* Form factors
** [[Socket AM2+]] with [[DDR2 SDRAM|DDR2]] for the 65&nbsp;nm Phenom and Athlon 7000 Series
** [[Socket AM3]] with either DDR2 or [[DDR3]] for Semprons and the 45&nbsp;nm Phenom II and Athlon II Series. They can also be used on AM3+ motherboards with DDR3. Note that, while all K10 Phenom Processors are backwards compatible with Socket AM2+ and [[Socket AM2]], some 45&nbsp;nm Phenom II Processors are only available for Socket AM2+. ''Lynx'' processors do not use either AM2+ nor AM3.
** [[Socket FM1]] with DDR3 for ''Lynx'' processors.
** [[Socket F]] with DDR2, DDR3 with ''Shanghai'' and later Opteron processors
* Instruction set additions and extensions
** New bit-manipulation [[Instruction (computer science)|instructions]] [[Bit Manipulation Instruction Sets|ABM]]: Leading Zero Count (LZCNT) and Population Count (POPCNT)
** New [[Streaming SIMD Extensions|SSE]] instructions named as ''SSE4a'': combined mask-shift instructions (EXTRQ/INSERTQ) and scalar streaming store instructions (MOVNTSD/MOVNTSS). These instructions are not found in Intel's [[SSE4]]
** Support for unaligned SSE load-operation instructions (which formerly required 16-byte alignment)<ref>{{cite news |last=Case |first=Loyd |title=AMD Unveils Barcelona Quad-Core Details |url=http://www.channelinsider.com/article/AMD+Unveils+Barcelona+QuadCore+Details/191008_2.aspx |publisher=Ziff Davis |access-date=2007-03-18}}{{dead link|date=June 2016|bot=medic}}{{cbignore|bot=medic}}</ref>
* Execution pipeline enhancements
** 128-bit wide [[Streaming SIMD Extensions|SSE]] units
** Wider L1 data cache interface allowing for two 128-bit loads per cycle (as opposed to two 64-bit loads per cycle with K8)
** Lower integer divide latency
** 512-entry indirect [[branch predictor]] and a larger return stack (size doubled from K8) and branch target buffer
** Side-Band Stack Optimizer, dedicated to perform increment/decrement of register stack pointer
** Fastpathed CALL and RET-Imm instructions (formerly microcoded) as well as MOVs from SIMD registers to general purpose registers
* Integration of new technologies onto CPU die:
** [[Multi-core (computing)|Four processor cores (Quad-core)]]
** Split [[power plane]]s for CPU core and memory controller/northbridge for more effective power management, first dubbed ''Dynamic Independent Core Engagement'' or ''D. I. C. E.'' by AMD and now known as ''Enhanced PowerNow!'' (also dubbed Independent Dynamic Core Technology), allowing the cores and northbridge (integrated memory controller) to scale power consumption up or down independently.<ref>{{cite news | url=http://www.hardocp.com/article.html?art=MTE0OCwsLGhlbnRodXNpYXN0 | title=AMD Next Generation Processor Technology Slides | publisher=[[HardOCP]] | date=2006-08-22}}</ref>
** Shutting down portions of the circuits in core when not in load, named "CoolCore" Technology.
* Improvements in the memory subsystem:
** Improvements in access latency:
*** Support for re-ordering loads ahead of other loads and stores
*** More aggressive [[instruction prefetch]]ing, 32 bytes instruction prefetch as opposed to 16 bytes in [[AMD K8|K8]]
*** DRAM prefetcher for buffering reads
*** Buffered burst writeback to RAM in order to reduce contention
** Changes in memory hierarchy:
*** Prefetch directly into L1 cache as opposed to L2 cache with K8 family
*** 32-way set associative L3 victim cache sized at least 2&nbsp;MB, shared between processing cores on a single die (each with 512 K&nbsp; of independent exclusive L2 cache), with a sharing-aware replacement policy.
*** Extensible L3 cache design, with 6&nbsp;MB planned for [[45&nbsp;nm]] process node, with the chips codenamed ''Shanghai''.
** Changes in address space management:
*** Two 64-bit independent memory controllers, each with its own physical address space; this provides an opportunity to better utilize the available bandwidth in case of random memory accesses occurring in heavily multi-threaded environments. This approach is in contrast to the previous "interleaved" design, where the two 64-bit data channels were bounded to a single common address space.
*** Larger Tagged Lookaside Buffers; support for 1 [[Gigabyte|GB]] page entries and a new 128-entry 2&nbsp;MB page TLB
*** 48-bit [[memory addressing]] to allow for 256 TB memory subsystems<ref name="amd10h">{{cite web|url=https://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf |title=BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors |access-date=2010-05-29 |page=24 |quote=Physical address space increased to 48 bits. |url-status=dead |archive-url=https://web.archive.org/web/20110609204027/http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf |archive-date=June 9, 2011 }}</ref>
*** Memory mirroring (alternatively mapped DIMM addressing),<ref>{{cite web
 | url = http://support.amd.com/TechDocs/42300_15h_Mod_10h-1Fh_BKDG.pdf#page=340
 | title = BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 10h-1Fh Processors
 | date = June 4, 2013 | access-date = January 25, 2015
 | publisher = [[Advanced Micro Devices]] | website = support.amd.com
 | format = PDF | page = 340
}}</ref> data poisoning support and Enhanced [[Reliability, availability and serviceability (computer hardware)|RAS]]
*** [[AMD-V Nested Paging]] for improved MMU virtualization, claimed to have decreasing world switch time by 25%.
* Improvements in system interconnect:
** [[HyperTransport]] retry support
** Support for HyperTransport 3.0, with HyperTransport Link unganging which creates 8 point-to-point links per socket.
* Platform-level enhancements with additional functionality:
** Five p-states allowing for automatic clock rate modulation
** Increased [[clock gating]]
** Official support for coprocessors via [[HyperTransport|HTX]] slots and vacant CPU sockets through [[HyperTransport]]: [[Torrenza]] initiative.

== Feature tables ==
===CPUs===
{{empty section|date=March 2023}} <!-- Template:AMD x86 CPU features was deleted per oldid=1142398499#Template:AMD_x86_CPU_features -->

===APUs===
[[Template:AMD APU features|APU features table]]

== Desktop ==

===Phenom models===

====''Agena'' (65 nm SOI, quad-core)====
* Four AMD K10 cores
* L1 cache: 64&nbsp;KB [[Instruction (computer science)|instruction]] and 64&nbsp;KB [[Data (computing)|data]]<ref name="BinaryPrefix">In this article, the conventional prefixes for computer memory denote base-2 values whereby "kilobyte" (KB) = 2<sup>10</sup> bytes.</ref> ([[Data (computing)|data]] + [[Instruction (computer science)|instructions]]) per core
* L2 cache: 512&nbsp;KB per core, full-speed
* L3 cache: 2&nbsp;MB shared between all cores
* Memory controller: dual channel DDR2-1066&nbsp;MHz with unganging option
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[AMD64]], [[Cool'n'Quiet]], [[NX bit]], [[AMD-V]]''
* [[Socket AM2+]], [[HyperTransport]] with 1600 to 2000&nbsp;MHz
* Power consumption ([[Thermal Design Power|TDP]]): 65, 95, 125 and 140 Watt
* First release
** November 19, 2007 (B2 Stepping)
** March 27, 2008 (B3 Stepping)
* Clock rate: 1800 to 2600&nbsp;MHz
* Models: [[List of AMD Phenom microprocessors#"Agena" (B2/B3, 65 nm, Quad-core)|Phenom X4 9100e - 9950]]

====''Toliman'' (65 nm SOI, tri-core)====
* Three AMD K10 cores
* L1 cache: 64&nbsp;KB instruction and 64&nbsp;KB data cache per core
* L2 cache: 512&nbsp;KB per core, full-speed
* L3 cache: 2&nbsp;MB shared between all cores
* Memory controller: dual channel DDR2-1066&nbsp;MHz with unganging option
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[AMD64]], [[Cool'n'Quiet]], [[NX bit]], [[AMD-V]]''
* [[Socket AM2+]], [[HyperTransport]] with 1600 to 1800&nbsp;MHz
* Power consumption ([[Thermal Design Power|TDP]]): 65 and 95 Watt
* First release
** March 27, 2008 (B2 Stepping)
** April 23, 2008 (B3 Stepping)
* Clock rate: 2100 to 2500&nbsp;MHz
* Models: [[List of AMD Phenom microprocessors#"Toliman" (B2/B3, 65 nm, Tri-core)|Phenom X3 8250e - 8850]]

===Phenom II models===

====''Thuban'' (45 nm SOI, hexa-core)====
* Six AMD K10 cores
* L1 cache: 64&nbsp;KB instructions and 64&nbsp;KB data per core
* L2 cache: 512&nbsp;KB per core, full-speed
* L3 cache: 6&nbsp;MB shared between all cores.
* Memory controller: dual channel DDR2-1066&nbsp;MHz (AM2+), dual channel DDR3-1333 (AM3) with unganging option
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[AMD64]], [[Cool'n'Quiet]], [[NX bit]], [[AMD-V]]''
* [[Socket AM2+]], [[Socket AM3]], [[HyperTransport]] with 1800 to 2000&nbsp;MHz
* Power consumption ([[Thermal Design Power|TDP]]): 95 or 125&nbsp;Watt
* First release
** 27 April 2010 (E0 Stepping)
* Clock rate: 2.6 - 3.3&nbsp;GHz; up to 3.7&nbsp;GHz with Turbo Core
* Models: [[List of AMD Phenom microprocessors#"Thuban" (E0, 45 nm, Hexa-core)|Phenom II X6 1035T, 1045T, 1055T, 1065T, 1075T, 1090T and 1100T]]

====''Zosma'' (45 nm SOI, quad-core)====
* Four AMD K10 cores harvested from Thuban with two cores disabled<ref name="list"/>
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[x86-64#AMD64|AMD64]], [[Cool'n'Quiet]]'', ''[[x86 virtualization#AMD virtualization (AMD-V)|AMD-V]]'', ''[[Turbo Core]]'' (AMD equivalent of [[Intel Turbo Boost]])
* Memory support: [[DDR2 SDRAM]] up to PC2-8500, [[DDR3 SDRAM]] up to PC3-10600 ([[Socket AM3]] only)
* Models: [[List of AMD Phenom microprocessors#"Zosma" (E0, 45 nm, Quad-core)|Phenom II X4 650T, 840T, 960T, 970]] <small>''(Thuban-based Zosma core, OEM Only, 970 has unlocked multiplier but w/o Turbo Core)''</small>

====''Deneb'' (45 nm SOI, quad-core)====
* Four AMD K10 cores
* L1 cache: 64&nbsp;KB instructions and 64&nbsp;KB data per core
* L2 cache: 512&nbsp;KB per core, full-speed
* L3 cache: 6&nbsp;MB shared between all cores. The 800 series have 2&nbsp;MB of its L3 Cache disabled due to defects.
* Memory controller: dual channel DDR2-1066&nbsp;MHz (AM2+), dual channel DDR3-1333 (AM3) with unganging option
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[AMD64]], [[Cool'n'Quiet]], [[NX bit]], [[AMD-V]]''
* [[Socket AM2+]], [[Socket AM3]], [[HyperTransport]] with 1800 to 2000&nbsp;MHz
* Power consumption ([[Thermal Design Power|TDP]]): 65, 95, 125 and 140 Watt
* First release
** 8 January 2009 (C2 Stepping)
* Clock rate: 2500 to 3700&nbsp;MHz
* Models: [[List of AMD Phenom microprocessors#"Deneb" (C2/C3, 45 nm, Quad-core)|Phenom II X4 805 - 980 (except 840 and 850)]]

====42 TWKR Limited Edition (45 nm SOI, quad-core)====
AMD released a limited edition Deneb-based processor to extreme [[Overclocking|overclockers]] and partners. Fewer than 100 were manufactured.

The "42" officially represents four cores running at 2&nbsp;GHz, but is also a reference to [[the answer to life, the universe, and everything]] from ''[[The Hitchhiker's Guide to the Galaxy]]''.<ref>{{Cite web|url=http://www.legitreviews.com/article/1009/2/|title = Legit Reviews - Technology News & Reviews| date=27 June 2022 }}</ref>

* Four AMD K10 cores
* Models: [[List of AMD Phenom microprocessors#Phenom II 42 TWKR (C2, 45 nm, Quad-core, Limited Edition)|Phenom II 42 TWKR]]

====''Propus'' (45 nm SOI, quad-core)====
* Four AMD K10 cores harvested from Deneb with L3 cache disabled<ref name="list"/>
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[Cool'n'Quiet]], [[AMD-V]]''
* Memory support: [[DDR2 SDRAM]] up to PC2-8500 (DDR2-1066&nbsp;MHz), [[DDR3 SDRAM]] up to PC3-10600 (DDR3-1333&nbsp;MHz) ([[Socket AM3]] only)
* Models: [[List of AMD Phenom microprocessors#"Propus" (C3, 45 nm, Quad-core)|Phenom II X4 840 and 850]]

====''Heka'' (45 nm SOI, tri-core)====
* Three AMD K10 cores using chip harvesting technique, with one core disabled
* L1 cache: 64&nbsp;KB instructions and 64&nbsp;KB data per core
* L2 cache: 512&nbsp;KB per core, full-speed
* L3 cache: 6&nbsp;MB shared between all cores
* Memory controller: dual channel DDR2-1066&nbsp;MHz (AM2+), dual channel DDR3-1333 (AM3) with unganging option
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[AMD64]], [[Cool'n'Quiet]], [[NX bit]], [[AMD-V]]''
* [[Socket AM3]], [[HyperTransport]] with 2000&nbsp;MHz
* Power consumption ([[Thermal Design Power|TDP]]): 65 and 95 Watt
* First release
** 9 February 2009 (C2 Stepping)
* Clock rate: 2500 to 3000&nbsp;MHz
* Models: [[List of AMD Phenom microprocessors#"Heka" (C2/C3, 45 nm, Tri-core)|Phenom II X3 705e - 740]]

====''Callisto'' (45 nm SOI, dual-core)====
* Two AMD K10 cores using chip harvesting technique, with two cores disabled
* L1 cache: 64&nbsp;KB instructions and 64&nbsp;KB data per core
* L2 cache: 512&nbsp;KB per core, full-speed
* L3 cache: 6&nbsp;MB shared between all cores
* Memory controller: dual channel DDR2-1066&nbsp;MHz (AM2+), dual channel DDR3-1333 (AM3) with unganging option
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[AMD64]], [[Cool'n'Quiet]], [[NX bit]], [[AMD-V]]''
* [[Socket AM3]], [[HyperTransport]] with 2000&nbsp;MHz
* Power consumption ([[Thermal Design Power|TDP]]): 80 Watt
* First release
** 1 June 2009 (C2 Stepping)
* Clock rate: 3000 to 3500&nbsp;MHz
* Models: [[List of AMD Phenom microprocessors#"Callisto" (C2/C3, 45 nm, Dual-core)|Phenom II X2 545 - 570]]

====''Regor'' (45 nm SOI, dual-core)====
* Two AMD K10 cores
* Some are chip harvests from Propus or Deneb with two cores disabled<ref name="list"/>
* Most Regor-based processors feature double the L2 cache per core (1 MB) as other Athlon II and Phenom II processors.
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[Cool'n'Quiet]]'', ''[[x86 virtualization#AMD virtualization (AMD-V)|AMD-V]]''
* Memory support: [[DDR2 SDRAM]] up to PC2-8500, [[DDR3 SDRAM]] up to PC3-8500 (DDR3-1066&nbsp;MHz) ([[Socket AM3]] only)
* Models: [[List of AMD Phenom microprocessors#"Regor" (C3, 45 nm, Dual-core)|Phenom II X2 511 and 521]]

===Athlon X2 models===

====''Kuma'' (65 nm SOI, dual-core)====

* Two AMD K10 cores harvested from Agena with two cores disabled<ref name="list">{{Cite web|url=https://docs.google.com/spreadsheets/d/19Ms49ip5PBB7nYnf5urxsySvH-Sdy6liE2EBDaB8b54|title = List of Unlockable AMD CPUs}}</ref>
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[Cool'n'Quiet]], [[AMD-V]]''<ref name="archii">{{cite web|url=https://www.amd.com/us/products/desktop/processors/athlon-ii-x2/Pages/athlon-ii-key-features.aspx |title=AMD Athlon II Key Architectural Features |publisher=[[Advanced Micro Devices]] |access-date=July 8, 2010 |url-status=dead |archive-url=https://web.archive.org/web/20101202095247/http://www.amd.com/us/products/desktop/processors/athlon-ii-x2/Pages/athlon-ii-key-features.aspx |archive-date=December 2, 2010 }}</ref>
* Models: [[List of AMD Athlon X2 microprocessors#"Kuma" (B3, 65 nm)|Athlon X2 6500 - 7850]]

====''Regor/Deneb'' (45 nm SOI, dual-core)====

* Two AMD K10 cores. Some 5000 series processors are chip harvests from Propus or Deneb; All 5200 series chips are harvests, each has two cores disabled<ref name="list"/>
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[Cool'n'Quiet]], [[AMD-V]]''<ref name="archii"/>
* Models: [[List of AMD Athlon X2 microprocessors#"Regor/Deneb" (C2, 45 nm)|Athlon X2 5000+ and 5200+]]

===Athlon II Models===

====''Zosma'' (45 nm SOI, quad-core)====
* Four AMD K10 cores harvested from Thuban with two cores disabled<ref name="list"/>
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[x86-64#AMD64|AMD64]], [[Cool'n'Quiet]]'', ''[[x86 virtualization#AMD virtualization (AMD-V)|AMD-V]]'', ''[[Turbo Core]]'' (AMD equivalent of [[Intel Turbo Boost]])
* Memory support: [[DDR2 SDRAM]] up to PC2-8500, [[DDR3 SDRAM]] up to PC3-10600 ([[Socket AM3]] only)
* Models: [[List of AMD Athlon II microprocessors#"Zosma" (E0, 45 nm, Quad-core)|Athlon II X4 640[T]]]

====''Propus'' (45 nm SOI, quad-core)====
* Four AMD K10 cores<ref>[http://www.pcgameshardware.de/aid,691707/Athlon-II-Viele-neue-Exemplare-der-neuen-Einsteiger-Prozessoren-von-AMD/CPU/News/ Athlon II: Viele neue Exemplare der neuen Einsteiger-Prozessoren von AMD]</ref><ref>[http://www.dinoxpc.com/News/news.asp?ID_News=17475&What=News&tt=In+arrivo+nuovi+processori+Athlon+II+da+AMD In arrivo nuovi processori Athlon II da AMD] {{webarchive |url=https://web.archive.org/web/20110710130651/http://www.dinoxpc.com/News/news.asp?ID_News=17475&What=News&tt=In+arrivo+nuovi+processori+Athlon+II+da+AMD |date=July 10, 2011 }}</ref>
* L1 cache: 64&nbsp;KB instructions and 64&nbsp;KB data per core
* L2 cache: 512&nbsp;KB per core, full-speed
* Memory controller: dual channel DDR2-1066&nbsp;MHz (AM2+), dual channel DDR3-1333 (AM3) with unganging option
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[AMD64]], [[Cool'n'Quiet]], [[NX bit]], [[AMD-V]]''
* [[Socket AM3]], [[HyperTransport]] with 2000&nbsp;MHz
* Power consumption (TDP): 45 Watt or 95 Watt
* First release
** September 2009 (C2 Stepping)
* Clock rate: 2200 - 3100&nbsp;MHz
* Models: [[List of AMD Athlon II microprocessors#"Propus" (C2/C3, 45 nm, Quad-core)|Athlon II X4 600e - 650]]

====''Rana'' (45 nm SOI, tri-core)====
* Three [[AMD K10]] cores chip harvested from Propus or Deneb with one core disabled<ref name="list"/>
* L1 [[CPU cache|cache]]: 64 [[Kilobyte|kB]] + 64 kB ([[Data (computing)|data]] + [[Instruction (computer science)|instructions]]) per core
* L2 cache: 512 kB per core, full-speed
* Memory controller: dual channel DDR2-1066&nbsp;MHz (AM2+), dual channel DDR3-1333 (AM3) with unganging option
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[AMD64]], [[Cool'n'Quiet]], [[NX bit]], [[AMD-V]]''
* [[Socket AM3]], [[HyperTransport]] with 2&nbsp;GHz
* Die Size: 169&nbsp;mm<sup>2</sup><ref name="phenomIIx6cpulist">{{Cite web |url=http://www.lostcircuits.com/mambo//index.php?option=com_content&task=view&id=81&Itemid=42&limit=1&limitstart=1 |title=AMD Phenom II X6: Thuban the Dragon |access-date=2018-03-29 |archive-url=https://web.archive.org/web/20140716080858/http://www.lostcircuits.com/mambo//index.php?option=com_content&task=view&id=81&Itemid=42&limit=1&limitstart=1 |archive-date=2014-07-16 |url-status=dead }}</ref>
* Power consumption (TDP): 45 Watts or 95 Watts
* First release
** October 2009 (Stepping C2)
* Clock rate: 2.2–3.4&nbsp;GHz
* Models: [[List of AMD Athlon II microprocessors#"Rana" (C2/C3, 45 nm, Tri-core)|Athlon II X3 400e - 460]]

====''Regor'' (45 nm SOI, dual-core)====
* Two AMD K10 cores
* L1 cache: 64&nbsp;KB instructions and 64&nbsp;KB data per core
* L2 cache: 1024&nbsp;KB per core, full-speed
* Memory controller: dual channel DDR2-1066&nbsp;MHz (AM2+), dual channel DDR3-1333 (AM3) with unganging option
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[AMD64]], [[Cool'n'Quiet]], [[NX bit]], [[AMD-V]]''
* [[Socket AM3]], [[HyperTransport]] with 2000&nbsp;MHz
* Power consumption ([[Thermal Design Power|TDP]]): 65 Watt
* First release
** June 2009 (C2 Stepping)
* Clock rate: 1600 - 3600&nbsp;MHz
* Models: [[List of AMD Athlon II microprocessors#"Regor" (C2/C3, 45 nm, Dual-core)|Athlon II X2 250u - 280]]

====''Sargas'' (45 nm SOI, single-core)====
* Single AMD K10 core harvest from Regor with one core disabled<ref name="list"/>
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[Cool'n'Quiet]], [[AMD-V]]''
* Memory support: [[DDR2 SDRAM]] up to PC2-6400, [[DDR3 SDRAM]] up to PC3-8500 ([[Socket AM3]] only)
* Models: [[List of AMD Athlon II microprocessors#"Sargas" (C2/C3, 45 nm, Single-core)|Athlon II 160u and 170u]]

====''Lynx'' (32 nm SOI, dual or quad-core)====
* Two or four AMD K10 cores with no L3 cache
* APUs without graphics. [[AMD 10h#Lynx (32 nm SOI with Immersion Lithography)|See below.]]
* Models: [[List of AMD accelerated processing unit microprocessors#Lynx: "Llano" (2011)|Athlon II X2 221 to Athlon II X4 651K]]

===Sempron models===

====''Sargas'' (45 nm SOI, single-core)====

* Single [[AMD K10]] core chip harvested from Regor with one core disabled<ref name="list"/>
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[Cool'n'Quiet]], [[AMD-V]]''
* Models: [[List of AMD Sempron microprocessors#"Sargas" (Socket AM3, Single-core, C2 & C3, 45 nm)|Sempron 130-150]]

===Sempron X2 models===

====''Regor'' (45 nm SOI, dual-core)====

* Two AMD K10 cores
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[Cool'n'Quiet]], [[AMD-V]]''
* Models: [[List of AMD Sempron microprocessors#"Regor" (Socket AM3, Dual-core, C3, 45 nm)|Sempron X2 180 and 190]]

====''Lynx'' (32 nm SOI, dual-core)====
* Two AMD K10 cores with no L3 cache
* APUs without graphics. [[AMD 10h#Lynx (32 nm SOI with Immersion Lithography)|See below.]]
* Models: [[List of AMD accelerated processing unit microprocessors#Lynx: "Llano" (2011)|Sempron X2 198]]

=== ''Llano'' "APUs" ===

====''Lynx'' (32 nm SOI, dual or quad-core)====

The first generation desktop APUs based on the K10 microarchitecture were released in 2011 (some models do not provide graphics capability, such as the ''Lynx'' Athlon II and Sempron X2).

* [[Semiconductor device fabrication|Fabrication]] 32&nbsp;nm on [[GlobalFoundries]] [[Silicon on insulator|SOI]] process 
* [[Socket FM1]]
* [[Die (integrated circuit)|Die]] size: 228&nbsp;mm<sup>2</sup>, with 1.178&nbsp;billion transistors<ref>{{cite web |url= http://www.brightsideofnews.com/news/2012/5/28/amd-comes-clean-on-transistor-numbers-with-fx2c-fusion-processors.aspx |title= AMD Comes Clean on Transistor Numbers With FX, Fusion Processors |author= Theo Valich |date= 28 May 2012 |access-date= 23 August 2013}}</ref><ref name="AnandTech_TrinityReview">{{cite web |url= http://www.anandtech.com/show/6332/amd-trinity-a10-5800k-a8-5600k-review-part-1 |title=AMD A10-5800K & A8-5600K Review: Trinity on the Desktop, Part 1 |author= Anand Lal Shimpi |date= 27 September 2012 |access-date= 23 August 2013}}</ref>
* AMD K10 cores with no L3 cache
* GPU: [[TeraScale 2]]
* All A and E series models feature ''Redwood''-class integrated graphics on die (''BeaverCreek'' for the dual-core variants and ''WinterPark'' for the quad-core variants). Sempron and Athlon models exclude integrated graphics.<ref name="athlon">{{cite web |url=http://www.cpu-world.com/news_2011/2011081701_AMD_launches_A-Series_and_the_first_32nm_Athlon_II_X4_CPUs.html |title=AMD launches A-Series and the first 32nm Athlon II X4 CPUs |access-date=2013-11-10}}</ref>
* Support for up to four [[DIMM]]s of up to [[DDR3]]-1866 memory
* 5&nbsp;GT/s [[UMI AMD|UMI]]
* Integrated [[PCIE#PCI Express 2.0|PCIe 2.0]] controller
* Select models support Turbo Core technology for faster CPU operation when the thermal specification permits
* Select models support Hybrid Graphics technology to assist a discrete Radeon HD 6450, 6570, or 6670 discrete graphics card. This is similar to the current Hybrid CrossFireX technology available in the AMD 700 and 800 chipset series
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[x86-64#AMD64|AMD64]], [[Cool'n'Quiet]]'', ''[[AMD-V]]''
* Models: [[List of AMD accelerated processing unit microprocessors#Lynx: "Llano" (2011)|Lynx desktop APUs and CPUs]]

== Mobile ==

=== Turion II (Ultra) models ===

==== "''Caspian''" (45nm SOI, dual-core) ====

* [[AMD mobile platform#Tigris platform (2009)|'''''Tigris'' platform''']]<ref name="FPUWidth02">{{cite web |url=https://www.amd.com/us/products/notebook/platforms/home/next-gen/Pages/platform-next-gen-notebooks.aspx |title=The 2009 AMD Mainstream Platform |publisher=Amd.com |access-date=2014-04-30 |archive-url=https://web.archive.org/web/20120527143416/http://www.amd.com/us/products/notebook/platforms/home/next-gen/Pages/platform-next-gen-notebooks.aspx |archive-date=2012-05-27 |url-status=dead }}</ref>
* Two AMD K10 cores
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[AMD-V]], [[PowerNow!]]''
* Memory support: [[DDR2 SDRAM]] (Up to 800&nbsp;MHz)
* Models: [[List of AMD mobile microprocessors#"Caspian" (45 nm)|Turion II Ultra M600 to M660]]

=== Turion II models ===

==== "''Caspian''" (45nm SOI, dual-core) ====

* '''''Tigris'' platform'''
* Two AMD K10 cores
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[AMD-V]], [[PowerNow!]]''
* Memory support: [[DDR2 SDRAM]] (Up to 800&nbsp;MHz)
* Models: [[List of AMD mobile microprocessors#Caspian" (45 nm)|Turion II M500 TO M560]]

==== "''Champlain''" (45nm SOI, dual-core) ====

* [[AMD mobile platform#Danube platform (2010)|'''''Danube'' platform''']]<ref name="M880Gamdcom">{{cite web|url=https://www.amd.com/us/products/notebook/platforms/home/amd-m880g/Pages/m880g-chipset.aspx |title=AMD M880G Chipset |publisher=Amd.com |access-date=2014-04-30}}</ref><ref name="FPUWidth03">{{cite web|url=https://www.amd.com/us/products/notebook/platforms/home/2010-mainstream/Pages/2010-mainstream-platform.aspx |title=The 2010 AMD Mainstream Platform |publisher=Amd.com |access-date=2014-04-30}}</ref>
* Two AMD K10 cores
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[AMD-V]], [[PowerNow!]]''
* Memory support: [[DDR3 SDRAM]], [[DDR3 SDRAM#Overview|DDR3L SDRAM]] (Up to 1333&nbsp;MHz)
* Models: [[List of AMD mobile microprocessors#Champlain (45 nm)|Turion II models]]

=== Athlon II models ===

==== "''Caspian''" (45nm SOI, dual-core) ====

* '''''Tigris'' platform'''
* Two AMD K10 cores
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[AMD-V]], [[PowerNow!]]''
* Memory support: [[DDR2 SDRAM]] (Up to 800&nbsp;MHz)
* Models: [[List of AMD mobile microprocessors#Caspian" (45 nm)|Athlon II M300 to M360]]

==== "''Champlain''" (45nm SOI, dual-core) ====

* '''''Danube'' platform'''
* Two AMD K10 cores
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[AMD-V]], [[PowerNow!]]''
* Memory support: [[DDR3 SDRAM]], [[DDR3 SDRAM#Overview|DDR3L SDRAM]] (Up to 1333&nbsp;MHz)
* Models: [[List of AMD mobile microprocessors#Champlain (45 nm)|Athlon II models]]

=== Sempron models ===

==== "''Caspian''" (45nm SOI, single-core) ====

* '''''Tigris'' platform'''
* Single AMD K10 core
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[AMD-V]], [[PowerNow!]]''
* Memory support: [[DDR2 SDRAM]] (Up to 800&nbsp;MHz)
* Models: [[List of AMD mobile microprocessors#Caspian" (45 nm)|Sempron M100 to M140]]

=== Turion II Neo models ===

==== "''Geneva''" (45nm SOI, dual-core) ====

* '''''Nile'' platform'''<ref name="M880Gamdcom"/><ref name="FPUWidth04">{{cite web |url=https://www.amd.com/us/products/notebook/platforms/home/2010-ultrathin/Pages/2010-ultrathin-platform.aspx |title=The 2010 AMD Ultrathin Platform |publisher=Amd.com |access-date=2014-04-30 |archive-url=https://web.archive.org/web/20121031040503/http://www.amd.com/us/products/notebook/platforms/home/2010-ultrathin/Pages/2010-ultrathin-platform.aspx |archive-date=2012-10-31 |url-status=dead }}</ref>
* Two AMD K10 cores
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[AMD-V]], [[PowerNow!]]''
* Memory support: [[DDR3 SDRAM]], [[DDR3 SDRAM#Overview|DDR3L SDRAM]] (Up to 1066&nbsp;MHz)
* Models: [[List of AMD mobile microprocessors#"Geneva" (45 nm)|Turion II Neo models]]

=== Athlon II Neo models ===

==== "''Geneva''" (45nm SOI, dual-core) ====

* '''''Nile'' platform'''
* Two AMD K10 cores
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[AMD-V]], [[PowerNow!]]''
* Memory support: [[DDR3 SDRAM]], [[DDR3 SDRAM#Overview|DDR3L SDRAM]] (Up to 1066&nbsp;MHz)
* Models: [[List of AMD mobile microprocessors#"Geneva" (45 nm)|Athlon II Neo models]]

==== "''Geneva''" (45nm SOI, single-core) ====

* '''''Nile'' platform'''
* Single AMD K10 core
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[AMD-V]], [[PowerNow!]]''
* Memory support: [[DDR3 SDRAM]], [[DDR3 SDRAM#Overview|DDR3L SDRAM]] (Up to 1066&nbsp;MHz)
* Models: [[List of AMD mobile microprocessors#"Geneva" (45 nm)|Athlon II K125 and K145]]

=== V models ===

==== "''Geneva''" (45nm SOI, single-core) ====

* '''''Nile'' platform'''
* Single AMD K10 core
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[AMD-V]], [[PowerNow!]]''
* Memory support: [[DDR3 SDRAM]], [[DDR3 SDRAM#Overview|DDR3L SDRAM]] (Up to 1066&nbsp;MHz)
* Models: [[List of AMD mobile microprocessors#"Geneva" (45 nm)|V 105]]

==== "''Champlain''" (45nm SOI, single-core) ====

* '''''Danube'' platform'''
* Single AMD K10 core
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[AMD-V]], [[PowerNow!]]''
* Memory support: [[DDR3 SDRAM]], [[DDR3 SDRAM#Overview|DDR3L SDRAM]] (Up to 1333&nbsp;MHz)
* Models: [[List of AMD mobile microprocessors#Champlain (45 nm)|V 120 to 160]]

=== Phenom II models ===

==== "''Champlain''" (45nm SOI, quad-core) ====

* '''''Danube'' platform'''
* Four AMD K10 cores
* Unlike desktop models, mobile Phenom II models do not have L3 cache
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[AMD-V]], [[PowerNow!]]''
* Memory support: [[DDR3 SDRAM]], [[DDR3 SDRAM#Overview|DDR3L SDRAM]] (Up to 1333&nbsp;MHz)
* Models: [[List of AMD mobile microprocessors#Phenom II|Phenom II models]]

==== "''Champlain''" (45nm SOI, tri-core) ====

* '''''Danube'' platform'''
* Three AMD K10 cores
* Unlike desktop models, mobile Phenom II models do not have L3 cache
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[AMD-V]], [[PowerNow!]]''
* Memory support: [[DDR3 SDRAM]], [[DDR3 SDRAM#Overview|DDR3L SDRAM]] (Up to 1333&nbsp;MHz)
* Models: [[List of AMD mobile microprocessors#Phenom II|Phenom II models]]

==== "''Champlain''" (45nm SOI, dual-core) ====

* '''''Danube'' platform'''
* Two AMD K10 cores
* Unlike desktop models, mobile Phenom II models do not have L3 cache
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[AMD-V]], [[PowerNow!]]''
* Memory support: [[DDR3 SDRAM]], [[DDR3 SDRAM#Overview|DDR3L SDRAM]] (Up to 1333&nbsp;MHz)
* Models: [[List of AMD mobile microprocessors#Phenom II|Phenom II models]]

=== ''Llano'' APUs ===

==== "''Sabine''" (32nm SOI, dual or quad-core) ====

* [[Semiconductor device fabrication|Fabrication]] 32&nbsp;nm on GlobalFoundries' SOI process
* [[Socket FS1]]
* Two or four upgraded K10 cores codenamed ''Husky''{{Citation needed|date=May 2014}} (K10.5{{Citation needed|date=May 2014}}) with no L3 cache, and with ''Redwood''-class integrated graphics on die (''WinterPark'' for the dual-core variants and ''BeaverCreek'' for the quad-core variants)
* Integrated [[PCIE#PCI Express 2.0|PCIe 2.0]] controller
* GPU: [[TeraScale 2]]
* Select models support Turbo Core technology for faster CPU operation when the thermal specification permits
* 2.5&nbsp;GT/s UMI
* [[List of instruction sets|ISA extensions]]: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSE4a]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[NX bit]], [[AMD64]], [[AMD-V]], [[PowerNow!]]''
* Support for 1.35&nbsp;V [[DDR3L]]-1333 memory, in addition to regular 1.5&nbsp;V [[DDR3]] memory specified
* Models: [[List of AMD accelerated processing unit microprocessors#Sabine: "Llano" (2011)|''Sabine'' mobile APUs]]

== Server ==

There are two generations of K10-based processors for servers: Opteron [[Opteron#Opteron (65 nm SOI)|65 nm]] and [[Opteron#Opteron (45 nm SOI)|45 nm]].

==Successor==
{{Main|AMD Fusion|Bulldozer (microarchitecture)|AMD Bobcat}}
AMD discontinued further development of K10 based CPUs after Thuban, choosing to focus on [[AMD Fusion|Fusion]] products for mainstream desktops and laptops and [[Bulldozer (microarchitecture)|Bulldozer]] based products for the performance market. However, within the Fusion product family, [[AMD Accelerated Processing Unit|APUs]] such as the first generation A4, A6 and A8-series chips (Llano APUs) continued to use K10-derived CPU cores in conjunction with a Radeon graphics core. K10 and its derivatives were phased out of production by the introduction of Trinity-based APUs in 2012, which replaced the K10 cores in the APU with Bulldozer-derived cores.

== Family 11h and 12h derivatives ==

=== {{anchor|Family 11h|11h}} Turion X2 Ultra Family 11h ===
{{further|AMD mobile platform#Puma platform (2008)|AMD Turion#Turion X2 Ultra}}
The Family 11h microarchitecture was a mixture of both K8 and K10 designs with lower power consumption for laptop that was marketed as Turion X2 Ultra and was later replaced by completely K10-based designs.<ref name="leon"/>

=== {{anchor|Family 12h|12h}} Fusion Family 12h ===
{{further|AMD Accelerated Processing Unit#Llano}}
The Family 12h microarchitecture is a derivative of the K10 design:<ref name=fusion_apu_arch>{{cite web|author1=David Kanter|title=AMD Fusion Architecture and Llano|url=http://www.realworldtech.com/fusion-llano/2/|website=Real World Tech|access-date=12 September 2015|date=27 June 2011}}</ref><ref name="fusion_apu_mem">{{cite web |author1=Pierre Boudier |author2=Graham Sellers |date=June 2011 |title=Memory System on Fusion APUs - The Benefits of Zero Copy |url=https://developer.amd.com/wordpress/media/2013/06/1004_final.pdf |publisher=AMD Fusion Developer Summit}}</ref>
* Both CPU and GPU were re-used to avoid complexity and risk
* Distinct Software and Physical integration makes Fusion (APU) microarchitectures different
* Power-saving improvements including [[clock gating]]
* Improvements to hardware pre-fetcher
* Redesigned memory controller
* 1MB L2 cache per core
* No L3 cache
* Two new buses for on-die GPU to access memory (called Onion and Garlic interfaces)
** AMD Fusion Compute Link (Onion) – interfaces to CPU cache and coherent system memory (see [[cache coherence]])
** Radeon Memory Bus (Garlic) – dedicated non-coherent interface connected directly to memory

==Media discussions==
''Note'': These media discussions are listed in ascending date of publication.
* {{cite news | url=http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2565 | title=AMD CTO speaks about future AMD technologies | publisher=AnandTech |date=2005-10-14}}
* {{cite news | url=http://techreport.com/etc/2005q4/amd-direction/index.x?pg=1 | title=AMD outlines Future Goals (mostly non-specific at this time) | publisher=TechReport | date=2005-10-17 | access-date=2006-08-19 | archive-url=https://web.archive.org/web/20061230235342/http://techreport.com/etc/2005q4/amd-direction/index.x?pg=1 | archive-date=2006-12-30 | url-status=dead }}
* {{cite news | url=http://news.cnet.com/2061-10791_3-6029475.html?part=rss&tag=6029475&subj=news | title=AMD eyes Z-RAM for dense caches | publisher=CNet News | date=2006-01-20}}
* {{cite news | url=http://hardware.slashdot.org/article.pl?sid=06/01/21/0730235 | title=AMD licenses Z-RAM | publisher=SlashDot | date=2006-01-21}}
* {{cite news | url=http://www.geek.com/chips/amds-k8l-to-double-fpu-units-in-2007-561620/ | title=AMD's K8L to double FPU units in 2007 | publisher=Geek.com | date=2006-02-24 | access-date=2015-06-07 | archive-date=2016-01-12 | archive-url=https://web.archive.org/web/20160112143623/http://www.geek.com/chips/amds-k8l-to-double-fpu-units-in-2007-561620/ | url-status=dead }}
* {{cite news | url=http://www.theinquirer.net/?article=30042 | archive-url=https://web.archive.org/web/20060312095143/http://www.theinquirer.net/?article=30042 | url-status=unfit | archive-date=March 12, 2006 | title=Rev G. and H. AMD64 chips Preliminary information | publisher=The Inquirer | date=2006-03-03}}
* {{cite news | url=http://www.digitimes.com/bits_chips/a20060314PR200.html | title=Interview with Henri Richard (Part 2) | publisher=DigiTimes | date=2006-03-14}}
* {{cite news | url=http://www.linuxelectrons.com/article.php/2006032009585692 | archive-url=https://web.archive.org/web/20061021152142/http://www.linuxelectrons.com/article.php/2006032009585692 | url-status=dead | archive-date=2006-10-21 | title=AMD demonstrates Hardware Coprocessor Offload | publisher=LinuxElectrons | date=2006-03-20}}
* {{cite news | url=http://www.theinquirer.net/?article=30539 | archive-url=https://web.archive.org/web/20160112143624/http://www.theinquirer.net/?article=30539 | url-status=unfit | archive-date=January 12, 2016 | title=Implementation of FPGA through coherent HTT | publisher= The Inquirer | date=2006-03-26}}
* {{cite news | url=http://www.reghardware.co.uk/2006/04/04/amd_k8l_roadmap/ | title=AMD's K8L 65 nm core due H1 07 | publisher=Reg Hardware | date=2006-04-04 | access-date=2007-04-19 | archive-url=https://web.archive.org/web/20070524105852/http://www.reghardware.co.uk/2006/04/04/amd_k8l_roadmap/ | archive-date=2007-05-24 | url-status=dead }}
* {{cite news | url=http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2734 | title=An AMD Update: Fab 36 Begins Shipments, Planning for 65 nm and AM2 Performance | publisher=AnandTech |date=2006-04-04}}
* {{cite news | url=http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2734 | title=Fab36 substantially converted to 65 nm by mid-2007 |publisher=AnandTech |date=2006-04-04}}
* {{cite news | url=http://www.theinquirer.net/?article=31761 | archive-url=https://web.archive.org/web/20060614165456/http://www.theinquirer.net/?article=31761 | url-status=unfit | archive-date=June 14, 2006 | title=AMD shows off details of K8L | publisher=The Inquirer | date=2006-05-16}}
* {{cite news | url=http://www.realworldtech.com/page.cfm?ArticleID=RWT060206035626 | title=AMD's K8L and 4x4 Preview | publisher=RealWorldtech | date=2006-06-02}}
* {{cite news | url=https://arstechnica.com/news.ars/post/20060602-6977.html | title=AMD K8L and 4X4 Technologies | publisher=ArsTechnica | date=2006-06-02}}
* {{cite news|url=http://www.pureoverclock.com/article37.html |title=AMD Quad-Core K8L & 4x4 Details |publisher=Pure OverClock |date=2006-06-03 |url-status=dead |archive-url=https://web.archive.org/web/20120209171346/http://www.pureoverclock.com/article37.html |archive-date=February 9, 2012 }}
* {{cite news | url=http://www.dailytech.com/article.aspx?newsid=3169 | title=Socket AM2 Forward Compatible With AM3 CPUs | publisher=DailyTech | date=2006-07-06 | url-status=dead | archive-url=https://web.archive.org/web/20070608124829/http://www.dailytech.com/article.aspx?newsid=3169 | archive-date=2007-06-08 }}
* {{cite news|url=http://theinquirer.net/default.aspx?article=32948 |title=K8L on schedule, due for release as early as Q1 07 |publisher=The Inquirer |date=2006-07-11 |url-status=unfit |archive-url=https://web.archive.org/web/20070906164558/http://www.theinquirer.net/default.aspx?article=32948 |archive-date=September 6, 2007 }}
* {{cite news | url=http://sourceware.org/ml/binutils/2006-07/msg00178.html | title=GNU binutils support for the new K10 instructions | publisher=SourceWare.org | date=2006-07-13}}
* {{cite news|url=http://www.xbitlabs.com/news/cpu/display/20060721230935.html |title=AMD Executives Confirm K8L to Arrive in Mid-2007 |publisher=X-bit labs |date=2006-07-21 |url-status=dead |archive-url=https://web.archive.org/web/20061126085327/http://www.xbitlabs.com/news/cpu/display/20060721230935.html |archive-date=2006-11-26 }}
* {{cite news|url=http://tech.moneycontrol.com/news/amd-to-demo-k8l-by-year-end/2073/india/ |title=AMD To Demo K8L By Year End |publisher=moneycontrol.com |date=2006-07-23 |url-status=dead |archive-url=https://web.archive.org/web/20070818110559/http://tech.moneycontrol.com/news/amd-to-demo-k8l-by-year-end/2073/india/ |archive-date=August 18, 2007 }}
* {{cite news|url=http://www.tgdaily.com/2006/08/15/amd_releases_socket_f_and_am2_opteron/ |archive-url=https://web.archive.org/web/20060821222334/http://www.tgdaily.com/2006/08/15/amd_releases_socket_f_and_am2_opteron/ |url-status=dead |archive-date=2006-08-21 |title=AMD intros new Opterons and promises 68 W quad-core CPUs |publisher=tgdaily.com |date=2006-08-15 }}
* {{cite news | url=http://www.crn.com/sections/breakingnews/dailyarchives.jhtml?articleId=191902502 | title=Next-Generation AMD Opteron Paves The Way For Quad-Core | publisher=crn.com | date=2006-08-15 | access-date=2007-04-19 | archive-url=https://web.archive.org/web/20120206213118/http://www.crn.com/sections/breakingnews/dailyarchives.jhtml?articleId=191902502 | archive-date=2012-02-06 | url-status=dead }}
* {{cite news|url=http://www.xbitlabs.com/articles/cpu/display/amd-k8l.html |title=AMD's Next Generation Microarchitecture Preview: from K8 to K8L |publisher=X-bit labs |date=2006-08-21 |url-status=dead |archive-url=https://web.archive.org/web/20060827101302/http://www.xbitlabs.com/articles/cpu/display/amd-k8l.html |archive-date=2006-08-27 }}
* {{cite news|url=http://theinquirer.net/default.aspx?article=34433 |title=AMD quad cores: the whole story unfolded |publisher=The Inquirer |date=2006-09-16 |url-status=unfit |archive-url=https://web.archive.org/web/20070519231817/http://www.theinquirer.net/default.aspx?article=34433 |archive-date=May 19, 2007 }}
* {{cite news|url=http://www.infoworld.com/article/07/02/07/07OPcurve_1.html |title=AMD reinvents the x86 |publisher=InfoWorld |date=2007-02-07 |url-status=dead |archive-url=https://web.archive.org/web/20081207170125/http://www.infoworld.com/article/07/02/07/07OPcurve_1.html |archive-date=December 7, 2008 }}
* {{cite news | url=http://www.realworldtech.com/page.cfm?ArticleID=RWT051607033728 | title=Inside Barcelona: AMD's Next Generation | publisher=RealWorldTech |date=2007-05-16}}

==See also==
* [[AMD K9]]
* [[Phenom (processor)]]
* [[Phenom II]]
* [[List of AMD Phenom microprocessors]]
* [[List of AMD Athlon X2 microprocessors]]

==References==
{{reflist|30em}}

==External links==
* [https://www.amd.com/ AMD Official Website]
* [https://web.archive.org/web/20070407094427/http://multicore.amd.com/us-en/quadcore/ AMD Quad-core processors introduction]
* [http://www.dvhardware.net/article2023.html DarkVision Hardware: AMD talks about K9, K10 future innovations]
* [https://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_543~111541,00.html Next-Generation AMD Opteron Processors Introduced with Record OEM Design Wins and Native Quad-Core Upgrade Path (Official AMD press release on 15 August 2006)]
* [http://pc.watch.impress.co.jp/docs/2006/0202/kaigai238.htm PC Watch report about K10 based on AMD Technology Analyst Day 2004 and 2005] {{in lang|ja}}
* [http://pc.watch.impress.co.jp/docs/2006/0119/kaigai233.htm PC Watch report about K10 based on Slides presented in Microprocessor Forum 2003] {{in lang|ja}}
* {{cite web|url=https://www.amd.com/us-en/assets/content_type/DownloadableAssets/PhilHesterAMDAnalystDayV2.pdf |title=Slides of AMD 2006 Technology Analyst Day: Official Introduction of K10 Microarchitecture |url-status=bot: unknown |archive-url=https://web.archive.org/web/20090326033327/http://www.amd.com/us-en/assets/content_type/DownloadableAssets/PhilHesterAMDAnalystDayV2.pdf |archive-date=2009-03-26 }}&nbsp;{{small|(2.17&nbsp;[[Megabyte|MB]])}}
* [http://support.amd.com/TechDocs/40546.pdf Software Optimization Guide for AMD Family 10h and 12h Processors]
* [https://web.archive.org/web/20061230235342/http://techreport.com/etc/2005q4/amd-direction/index.x?pg=1 TechReport: AMD outlines Future Goals]
* [http://www.tweaktown.com/forums/archive/index.php/t-9833.html TweakTown Discussions (2003)]
* [https://web.archive.org/web/20070821104528/http://www.xbitlabs.com/articles/cpu/display/amd-k10.html X-bit labs: AMD K10 Micro-Architecture]

{{AMD processors}}

[[Category:AMD x86 microprocessors|K10]]
[[Category:AMD microarchitectures|K10]]
[[Category:X86 microarchitectures]]
[[Category:Computer-related introductions in 2007]]