View source for 22 nm process

{{use mdy dates|date=March 2022}}
{{Semiconductor manufacturing processes}}
{{short description|Process in semiconductor device fabrication}}
The '''"22 nm" node''' is the process step following [[32 nm process|32 nm]] in [[CMOS]] [[MOSFET]] [[semiconductor device fabrication]]. It was first demonstrated by [[Semiconductor company|semiconductor companies]] for use in [[Random-access memory|RAM]] in 2008. In 2010, [[Toshiba]] began shipping 24&nbsp;nm [[flash memory]] chips, and [[Samsung Electronics]] began mass-producing 20&nbsp;nm flash memory chips. The first consumer-level [[central processing unit|CPU]] deliveries using a 22&nbsp;nm process started in April 2012 with the [[Intel]] [[Ivy Bridge (microarchitecture)|Ivy Bridge]] processors.

Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit;<ref name="urlNo More Nanometers – EEJournal">{{cite web |url=https://www.eejournal.com/article/no-more-nanometers/ |title=No More Nanometers – EEJournal |date=July 23, 2020 |format= }}</ref> neither gate length, metal pitch or gate pitch on a "22nm" device is twenty-two nanometers.<ref>{{cite web|url=https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html|title=A Brief History of Process Node Evolution|last=Shukla|first=Priyank|website=design-reuse.com|access-date=2019-07-09}}</ref><ref>{{cite web|url=https://www.extremetech.com/computing/184946-14nm-7nm-5nm-how-low-can-cmos-go-it-depends-if-you-ask-the-engineers-or-the-economists|title=14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists...|last=Hruska|first=Joel|website=[[ExtremeTech]]}}</ref><ref>{{cite web|url=https://wccftech.com/intel-losing-process-lead-analysis-7nm-2022/|title=Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022|website=wccftech.com|date=2016-09-10}}</ref><ref>{{cite web|url=https://www.eejournal.com/article/life-at-10nm-or-is-it-7nm-and-3nm/|title=Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms|website=eejournal.com|date=2018-03-12}}</ref> 

The [[International Technology Roadmap for Semiconductors|ITRS]] 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5&nbsp;nm (about twice the diameter of a [[silicon]] [[atom]]), which is the expected value at the 22&nbsp;nm node. This is an indication that CMOS scaling in this area has reached a wall at this point, possibly disturbing [[Moore's law]].

The '''20-nanometre''' node is an intermediate half-node [[die shrink]] based on the 22-nanometre process.

[[TSMC]] began mass production of 20{{nbsp}}nm nodes in 2014.<ref>{{cite web |title=20nm Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/20nm.htm |publisher=[[TSMC]] |access-date=30 June 2019}}</ref> The 22&nbsp;nm process was superseded by commercial [[14 nm process|14&nbsp;nm]] [[FinFET]] technology in 2014.

==Technology demos==
On August 18, 2008, [[AMD]], [[Freescale]], [[IBM]], [[STMicroelectronics]], [[Toshiba]], and the [[College of Nanoscale Science and Engineering]] (CNSE) announced that they jointly developed and manufactured a 22&nbsp;nm [[Static Random Access Memory|SRAM]] cell, built on a traditional six-[[transistor]] design on a 300&nbsp;mm [[Wafer (electronics)|wafer]], which had a memory cell size of just 0.1 [[Micrometre|μm]]<sup>2</sup>.<ref>{{Cite web |url=http://www.tgdaily.com/content/view/38941/135/ |title=TG Daily news report |access-date=2008-08-18 |archive-url=https://web.archive.org/web/20080819150858/http://www.tgdaily.com/content/view/38941/135/ |archive-date=2008-08-19 |url-status=dead }}</ref> The cell was printed using [[immersion lithography]].<ref>[http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=210101316 EETimes news report]</ref>

The 22&nbsp;nm node may be the first time where the gate length is not necessarily smaller than the technology node designation. For example, a 25&nbsp;nm gate length would be typical for the 22&nbsp;nm node.

On September 22, 2009, during the [[Intel Developer Forum#2009 events|Intel Developer Forum Fall 2009]], [[Intel]] showed a 22&nbsp;nm wafer and announced that chips with 22&nbsp;nm technology would be available in the second half of 2011.<ref>[https://www.engadget.com/2009/09/22/intel-announces-22nm-chips-for-2011/ Intel announces 22nm chips for 2011]</ref> SRAM cell size is said to be 0.092 μm<sup>2</sup>, smallest reported to date.

On January 3, 2010, Intel and [[Micron Technology]] announced the first in a family of 25&nbsp;nm [[NAND gate|NAND]] devices.

On May 2, 2011, Intel announced its first 22&nbsp;nm microprocessor, codenamed [[Ivy Bridge (microarchitecture)|Ivy Bridge]], using a [[FinFET]] technology called ''3-D [[tri-gate]]''.<ref>[http://newsroom.intel.com/docs/DOC-2032 Intel 22nm 3-D Tri-Gate Transistor Technology]</ref>

IBM's [[POWER8]] processors are produced in a 22&nbsp;nm [[Silicon on insulator|SOI]] process.<ref>[https://www.theregister.co.uk/2011/08/31/ibm_power_chip_roadmap_update/ IBM opens Power8 kimono (a little bit more)]</ref>

==Shipped devices==
* [[Toshiba]] announced that it was shipping 24&nbsp;nm [[flash memory]] NAND devices on August 31, 2010.<ref>[http://www.toshiba.co.jp/about/press/2010_08/pr3101.htm?from=RSS_PRESS&uid=20100831-1112e Toshiba launches 24nm process NAND flash memory]</ref>
* In 2010, [[Samsung Electronics]] began mass production of 64{{nbsp}}[[Gibibit|Gbit]] [[NAND flash]] memory chips using a 20&nbsp;nm process.<ref name="samsung-history">{{cite web |title=History |url=https://www.samsung.com/us/aboutsamsung/company/history/ |website=[[Samsung Electronics]] |publisher=[[Samsung]] |access-date=19 June 2019}}</ref>
* Also in 2010, [[Hynix]] introduced a 64{{nbsp}}Gbit NAND flash memory chip using a 20&nbsp;nm process.<ref>{{cite web |title=History: 2010s |url=https://www.skhynix.com/eng/about/history2010.jsp |website=[[SK Hynix]] |access-date=8 July 2019 |archive-date=29 April 2021 |archive-url=https://web.archive.org/web/20210429202547/https://www.skhynix.com/eng/about/history2010.jsp |url-status=dead }}</ref>
* On April 23, 2012, [[Intel Core]] i7 and Intel Core i5 processors based on Intel's [[Ivy Bridge (microarchitecture)|Ivy Bridge]] 22&nbsp;nm technology for series 7 chipsets went on sale worldwide.<ref>[http://semiaccurate.com/2012/04/23/intel-launches-ivy-bridge-amid-crushing-marketing-buzzwords/ Intel launches Ivy Bridge...]</ref> Volume production of 22&nbsp;nm processors began more than six months earlier, as confirmed by former [[Intel]] CEO Paul Otellini on October 19, 2011.<ref>[http://www.tomshardware.com/news/ivy-bridge-processor-release-22nm-3d-transistor,13753.html Tom's Hardware: Intel to Sell] [[Ivy Bridge (microarchitecture)|Ivy Bridge]] Late in Q4 2011</ref>
* On June 3, 2013, Intel started shipping Intel Core i7 and Intel Core i5 processors based on Intel's [[Haswell (microarchitecture)|Haswell]] microarchitecture in 22&nbsp;nm ''tri-gate'' [[FinFET]] technology for series 8 chipsets.<ref>{{Cite web |url=http://newsroom.intel.com/community/intel_newsroom/blog/2013/04/26/chip-shot-4th-generation-intel-core-coming-soon/ |title=4th Generation Intel Core Processors Coming Soon |access-date=2013-04-27 |archive-url=https://web.archive.org/web/20150209212845/http://newsroom.intel.com/community/intel_newsroom/blog/2013/04/26/chip-shot-4th-generation-intel-core-coming-soon/ |archive-date=2015-02-09 |url-status=dead }}</ref> Intel's 22nm process has a transistor density of 16.5 million transistors per square millimeter (MTr/mm2).<ref>{{cite web | url=https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review/3 | title=Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review }}</ref>

==References==
{{Reflist|30em}}

{{sequence
| prev=[[32 nm process|32&nbsp;nm]] ([[CMOS]])
| next=[[14 nm process|14&nbsp;nm]] ([[FinFET]])
| list=[[MOSFET]] [[Semiconductor device fabrication|manufacturing processes]]
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{{DEFAULTSORT:22 nanometre}}
[[Category:International Technology Roadmap for Semiconductors lithography nodes|*00022]]