View source for Zilog Z8000

{{Short description|16-bit microprocessor}}
{{Use dmy dates|date=March 2020|cs1-dates=y}}
{{Infobox CPU architecture
| name        = Zilog Z8000 architecture
| designer    = [[Zilog]]
| bits        = 16-bit
| introduced  = {{Start date and age|1979|df=yes}}
| version     = 
| design      = CISC
| type        = Register–Memory
| encoding    = 
| branching   = Condition register
| endianness  = 
| page size   = 
| extensions  = 
| open        = 
| predecessor = 
| successor   = [[Zilog Z80000|Z80000]]
| registers   = 16 × 16-bit general purpose<br>24-bit PC<br>16-bit status
| gpr         = 
| fpr         = 
}}
{{Infobox CPU
| name          = Zilog Z8001
| image         = M20 mb cpu.jpg
| image_size    = 180px
| alt           = 
| caption       = Z8001 on the motherboard of an Olivetti M20 computer
| designfirm    = Zilog
| produced-start = {{Start date and age|1979|df=yes}}
| version       = 
| type          = 
| encoding      = 
| endianness    =
| page size     = 
| instructions  =
| extensions    = 
| data-width    = 16 bits
| address-width = 23 bits
| open          = 
| registers     = 
| gpr           =
| fpr           = 
| pack1         = 48-pin DIP (8001)
| pack2         = 40-pin DIP (8002)
| transistors   = 17,500
}}

The '''Zilog Z8000''' is a [[16-bit computing|16-bit]] microprocessor architecture designed by [[Zilog]] and introduced in early 1979. Two chips were initially released, differing only in the width of the address bus; the Z8001 had a 23-bit bus while the Z8002 had a 16-bit bus.

Bernard Peuto designed the architecture, while [[Masatoshi Shima]] did the logic and physical implementation, assisted by a small group. In contrast to most designs of the era, the Z8000 does not use [[microcode]], which allowed it to be implemented in only 17,500 transistors. The Z8000 is not [[Zilog Z80|Z80]]-compatible, but includes a number of design elements from it, such as combining two registers into one with twice the number of bits. The Z8000 expanded on the Z80 by allowing two 16-bit registers to operate as a 32-bit register, or four to operate as a 64-bit register.

Although it saw some use in the early 1980s, it was never as popular as the Z80. It was released after the 16-bit [[Intel 8086|8086]] (April 1978) and the same time as the less-expensive [[Intel 8088|8088]], and only months before the [[Motorola 68000|68000]] (September 1979) with a 32-bit [[instruction set architecture]] and which is roughly twice as fast. The [[Zilog Z80000|Z80000]] was a 32-bit follow-on design that made it to a test sampling phase in 1986 without ever being released commercially.<ref>{{cite web |url=https://www.kranenborg.org/z8000/ |title=The Z8000 / Z80,000 / Z16C00 CPU homepage |accessdate=2024-11-10}}</ref>

==History==
===Z80===
In the early 1970s, [[Intel]]'s management saw the [[microprocessor]] not so much as a product on its own, but as a way to create demand for their other products like [[static RAM]] and [[ROM]]. A reorganization in early 1974 further diluted the role of the microprocessor in the company. The designer of the [[Intel 4004]] and [[Intel 8080]], [[Federico Faggin]], decided to leave the company and start one dedicated to microprocessor design. Faggin left on 31 October 1974, joined by [[Ralph Ungermann]] and, later, the logic designer [[Masatoshi Shima]].{{sfn|Slater|2007|pp=2-3}}

Initially working on a concept for a simple [[microcontroller]], Faggin eventually concluded that the economics of the industry demanded that they introduce a product at the high-end, not the low-end. This led to a new concept initially known as the "Super 80", but eventually emerging as the [[Zilog Z80]]. The Z80 was a significant advance on the 8080, running on a single +5V power supply and adding several nice features from the [[Motorola 6800]]. Released in 1976, it was soon a huge hit.{{sfn|Slater|2007|p=4}}

===16-bit design===
While Shima was still working on the Z80 layout, Faggin began considering its future replacement by a 16-bit design, with the goal of being the first company to bring a new 16-bit single-chip design to market.{{efn|Several multi-chip 16-bit microprocessors existed by this point, but they were all based on existing [[minicomputer]] designs and were generally too expensive for general use. Single-chip versions of these emerged, but they remained expensive.{{sfn|Slater|2007|pp=4,5}}}} He felt that expanding the Z80 to 16-bits was not appropriate, the larger [[computer word]] size meant that many more features could be offered in the [[instruction set]] and the deliberately simple instructions of earlier designs would lead to chips that would be outperformed by freshly-designed 16-bit designs.{{sfn|Slater|2007|pp=2,3}}

In January 1976, Faggin hired Bernard Peuto, formerly of [[Amdahl Corporation]]. Peuto had previously studied and published extensively on the topic of word length, instruction sets and code density. The initial meetings on the concept were held at the end of March, at which time Faggin told Peuto he wanted the architecture completed in three months. The instruction set was delivered on time, but then it was time to turn that into a complete design.{{sfn|Slater|2007|p=3}} Peuto's design included the ability to work with 8-, 16- and 32-bit data, flexible addressing modes, and dedicated coprocessor support.{{sfn|Slater|2007|p=6}}

It was during this time that Ungermann explained the economics of the chip industry to Peuto, which were strongly influenced by the size of the chip. At the time, most processors used 40-pin [[dual in-line package]]s (DIPs), but some used 28-pin packages for lower-cost systems, while others were using 48 or 64-pin packages for more powerful systems like minicomputers. The need to balance cost and power ultimately led to the idea of having two versions of the chip, the Z8001 with 23 [[address bus]] pins in a 48-pin chip, and the Z8002 with 16 address pins in a 40-pin chip.{{sfn|Slater|2007|p=6}}

In order to have a single instruction set that could be used on either design, they made the decision to use [[segmented memory]].{{sfn|Slater|2007|p=6}} In this concept, the basic instruction set uses 16-bit addresses, which could then be run on either version of the chip. To access larger amounts of memory, a separate set of instructions could set a 7-bit "segment number". On the 23-pin versions, the 7-bit segment number was sent out at the same time as the 16-bit base address, creating a single 23-bit address. This early design choice would ultimately have a profound effect on the desirability of the Z8000 series.{{sfn|Slater|2007|p=7}}

Shima would be responsible for turning the conceptual design into a physical one, and with the basic design completed, Shima first began considering it on 11 June 1976. At the time the system was to have eight 16-bit registers, and Shima began laying out such a design. But very late in the process the design team concluded that it needed more, and when they asked in October, Shima stated he had laid it out with enough room left over that they could double the number of registers.{{sfn|Slater|2007|p=9}}

===Introduction===
In June 1978, while Shima was still working on the design of the Z8000, Intel introduced the [[Intel 8086]]. Zilog had missed its chance to be the first company with a new, dedicated 16-bit design. In some ways the 8086 was similar to the Z8000, including the use of segmented memory, but in general it was a less advanced design with fewer [[processor register]]s and a much smaller maximum memory of 1&nbsp;[[megabyte]] rather than the 8000's 8&nbsp;MB.{{sfn|Slater|2007|p=9}}

It was not until early 1979 that production samples of the Z8000 were released. Zilog stated that the Z8001 and Z8002 were merely differently packaged versions of the same Z8000 chip, "the difference being achieved by a bonding option during manufacture".<ref name="pcw198107_zilog">{{ cite magazine | url=https://archive.org/details/PersonalComputerWorld1981-07/page/62/mode/2up | title=Zilog writes | magazine=Personal Computer World | last1=Pittman | first1=Phil | date=July 1981 | access-date=13 May 2024 | pages=62–63 }}</ref>

Even with 48 pins, there were not enough connections to allow for a complete 16-bit data bus and 24-bit address bus, as that would leave only 8 free pins, which is not nearly enough for various other interfacing needs like power, clocks and interrupts. To address this, the Z8001 multiplexed the address and data pins together. The first 16 pins of the 23-pin address bus were used on alternate cycles as a 16-bit data bus. This meant that every memory access took two complete memory cycles: first the address would be presented and had to be "latched" using external circuity, and then on the next cycle 16 bit of data would be read or written using the same pins.<ref>{{cite tech report |url=https://html.alldatasheet.net/html-pdf/1283758/ZILOG/Z8000/172/1/Z8000.html |title=Z8000}}</ref> This means the Z8000 would run roughly half as fast as something like the 68000, which had separate 16 data pins and 24 address pins on a larger 64-pin chip.{{Dubious|1=Multiplexed bus|reason=Multiplexed address/data bus does not necessarily slow down accesses. The address must be presented some time before the data can be read or written. The moment the address appears, the data bus is idle on most processors including the 68000.|date=March 2025}}

Zilog already had a strategy to deal with this problem, the Zilog 8010 memory controller. The 8010 automatically folded the 7 and 16-bit parts of the address back together into a single 23-bit address, as well as offering a number of memory mapping features that made it useful for supporting [[Computer multitasking|multitasking]] and [[virtual memory]]. However, the 8010 was not ready when the 8001 was introduced. This meant that for 18 months, Intel had a single-chip solution that could access 1&nbsp;MB, while the 8000 series was still practically limited to 64&nbsp;kB. The 8010 was eventually released almost a year later, and even then it required two chips to do what the 8086 did with one.{{sfn|Slater|2007|pp=7,8}}

The delays with the 8010 was particularly hurtful. In September 1979, [[Motorola]] introduced the [[Motorola 68000]], which had a complete 24-bit address bus, which allowed it to access up to 16&nbsp;MB without segmentation. It also offered all of the features Zilog advertised as being more advanced than the 8086, such as more registers and a wide set of addressing modes. The market generally chose Intel for lower-end offerings and the 68000 for the high-end. Shima left the company to return to Japan in 1980, and Faggin left shortly thereafter.{{sfn|Slater|2007|p=23}}

===Later versions===
The series was later expanded to include the Z8003 and Z8004 updated versions of the Z8001 and Z8002, respectively. These versions were designed to provide improved support for [[virtual memory]], adding new status registers to indicate [[segmentation fault]]s (test and set) and provide an abort capability.

==Architecture==
{| class="infobox" style="font-size:88%;width:30em;"
|-
|+ Z8001 registers
|- style="font-size:88%; text-align:center;"
| style="width:10px"| <sup>1</sup><sub>5</sub>
| style="width:10px"| <sup>1</sup><sub>4</sub>
| style="width:10px"| <sup>1</sup><sub>3</sub>
| style="width:10px"| <sup>1</sup><sub>2</sub>
| style="width:10px"| <sup>1</sup><sub>1</sub>
| style="width:10px"| <sup>1</sup><sub>0</sub>
| style="width:10px"| <sup>0</sup><sub>9</sub>
| style="width:10px"| <sup>0</sup><sub>8</sub>
| style="width:10px"| <sup>0</sup><sub>7</sub>
| style="width:10px"| <sup>0</sup><sub>6</sub>
| style="width:10px"| <sup>0</sup><sub>5</sub>
| style="width:10px"| <sup>0</sup><sub>4</sub>
| style="width:10px"| <sup>0</sup><sub>3</sub>
| style="width:10px"| <sup>0</sup><sub>2</sub>
| style="width:10px"| <sup>0</sup><sub>1</sub>
| style="width:10px"| <sup>0</sup><sub>0</sub>
| colspan="3" style="width:auto;text-align:left" | ''(bit position)''
|-
| colspan="16" | &nbsp;
| colspan="3" style="font-size:88%; color:gray; text-align:center" | Grouping
|-
| colspan="16" | '''Main registers'''
| style="font-size:88%; color:gray" | ''16-bit''
| style="font-size:88%; color:gray" | ''32-bit''
| style="font-size:88%; color:gray" | ''64-bit''
|-
| colspan="8" style="background:silver; text-align:center" |  RH0
| colspan="8" style="background:silver; text-align:center" |  RL0
| '''R0'''
| rowspan="2" style="vertical-align:middle" | '''RR0'''
| rowspan="4" style="vertical-align:middle; border-bottom-style:solid; border-width:thin; border-color:silver" | '''RQ0'''
|-
| colspan="8" style="background:silver; text-align:center" |  RH1
| colspan="8" style="background:silver; text-align:center" |  RL1
| '''R1'''
|-
| colspan="8" style="background:silver;text-align:center" |  RH2
| colspan="8" style="background:silver;text-align:center" |  RL2
| '''R2'''
| rowspan="2" style="vertical-align:middle" | '''RR2'''
|-
| colspan="8" style="background:silver;text-align:center" |  RH3
| colspan="8" style="background:silver;text-align:center" |  RL3
| '''R3'''
|-
| colspan="8" style="background:silver;text-align:center" |  RH4
| colspan="8" style="background:silver;text-align:center" |  RL4
| '''R4'''
| rowspan="2" style="vertical-align:middle" | '''RR4'''
| rowspan="4" style="vertical-align:middle; border-bottom-style:solid; border-width:thin; border-color:silver" | '''RQ4'''
|-
| colspan="8" style="background:silver;text-align:center" |  RH5
| colspan="8" style="background:silver;text-align:center" |  RL5
| '''R5'''
|-
| colspan="8" style="background:silver;text-align:center" |  RH6
| colspan="8" style="background:silver;text-align:center" |  RL6
| '''R6'''
| rowspan="2" style="vertical-align:middle" | '''RR6'''
|-
| colspan="8" style="background:silver;text-align:center" |  RH7
| colspan="8" style="background:silver;text-align:center" |  RL7
| '''R7'''
|-
| colspan="16" style="background:silver;text-align:center" | &nbsp;
| '''R8'''
| rowspan="2" style="vertical-align:middle" | '''RR8'''
| rowspan="4" style="vertical-align:middle; border-bottom-style:solid; border-width:thin; border-color:silver" | '''RQ8'''
|-
| colspan="16" style="background:silver;text-align:center" | &nbsp;
| '''R9'''
|-
| colspan="16" style="background:silver;text-align:center" | &nbsp;
| '''R10'''
| rowspan="2" style="vertical-align: middle" | '''RR10'''
|-
| colspan="16" style="background:silver;text-align:center" | &nbsp;
| '''R11'''
|-
| colspan="16" style="background:silver;text-align:center" | &nbsp;
| '''R12'''
| rowspan="2" style="vertical-align: middle" | '''RR12'''
| rowspan="4" style="vertical-align: middle" | '''RQ12'''
|-
| colspan="16" style="background:silver;text-align:center" | &nbsp;
| '''R13'''
|-
| colspan="16" style="background:silver;text-align:center" | Normal Stack Pointer Segment
| '''R14'''
| rowspan="2" style="vertical-align: middle" | '''RR14'''
|-
| colspan="16" style="background:silver;text-align:center" | Normal Stack Pointer Offset
| '''R15'''
|-
| colspan="16" style="background:silver;text-align:center" | System Stack Pointer Segment
| '''R14'''
|-
| colspan="16" style="background:silver;text-align:center" | System Stack Pointer Offset
| '''R15'''
|- 
| colspan="19" | '''Refresh register'''
|- style="background:silver; color:black; text-align:center"
| style="font-size:88%" | <sup>R</sup><sub>E</sub>
| colspan="6" style="text-align:center"| Rate
| colspan="8" style="text-align:center"| Row Address
|0
|style="background: white; text-align: left" | '''R'''efresh
|- 
| colspan="19" | '''Program status area pointer'''
|- style="background:silver; color:black; text-align:center"
| 0
| colspan="7" style="text-align:center"| Segment
| colspan="8" style="text-align:center"| 0 0 0 0 0 0 0 0
|style="background: white; text-align: left" | Segment
|- style="background:silver; color:black; text-align:center"
| colspan="8" style="text-align:center"| Upper offset
| colspan="8" style="text-align:center"| 0 0 0 0 0 0 0 0
|style="background: white; text-align: left" | Offset
|- 
| colspan="19" | '''Program counter'''
|- style="background:silver; color:black; text-align:center"
| 0
| colspan="7" style="text-align:center"| Segment
| colspan="8" style="text-align:center"| 0 0 0 0 0 0 0 0
| colspan="3" rowspan="2" style="background: white; color: black; vertical-align: middle; text-align: left"| '''P'''rogram '''C'''ounter
|- style="background: silver; color: black"
| style="text-align:center;" colspan="16"| Address
|- 
|colspan="19" | '''Status register'''
|- style="background:silver; color:black; text-align:center"
| [[Memory segmentation|S]]
| style="font-size:88%" | <sup>S</sup><sub>N</sub>
| E
| V
| M
| -
| -
| -
| [[Carry flag|C]]
| [[Zero flag|Z]]
| [[Sign flag|S]]
| style="font-size:88%" | <sup>[[Parity flag|P]]</sup><sub>[[Overflow flag|O]]</sub>
| [[Adjust flag|D]]
| [[Half-carry flag|H]]
| -
| -
|style="background: white; text-align: left" | '''F'''lags
|}

===Registers===
There are sixteen 16-bit [[Processor register|registers]], labeled R0 through R15. The registers can be concatenated into eight 32-bit registers, labeled RR0/RR2/../RR14, or into four 64-bit registers, labeled RQ0/RQ4/RQ8/RQ12. The first eight registers can be also subdivided into sixteen 8-bit registers, labeled RL0 though RL7 for the lower byte and RH0 through RH7 for the upper (high) byte. Register R15 is designated as [[stack (data structure)|stack]] [[pointer (computer programming)|pointer]]. On the Z8001, register R14 is used to include a fixed segment in the stack pointer, and the [[program counter]] is expanded to 32 bits to include a similar segment.

There is both a [[user mode]] ("normal") and a [[supervisor mode]], selected by bit 14 in the flag register. In supervisor mode, the stack registers point to the system stack and all privileged instructions are available. In user mode, the stack registers point to the normal stack and all privileged instructions will generate a fault. Having separate modes and stacks greatly adds to the performance of [[context switch]]es between user programs and an [[operating system]].<ref name="abramovitz1981">{{cite book | first1=Bob | last1=Abramovitz | first2=Janice | last2=Enger | first3=Curtis | last3=Ingraham | first4=Susanna | last4=Jacobson | first5=Patrick | last5=McGuire | title=Osborne 16-Bit Microprocessor Handbook | date=1981 | isbn=0-931988-43-8 | publisher=Osborne/McGraw-Hill }}</ref>{{rp|pages=6.1}}

[[File:Zilog_Z8002_die.JPG|right|180px|thumb|[[Die (integrated circuit)|Die]] of Zilog Z8002]]

===Memory handling===
Like the Z80, the Z8000 includes a system to automatically refresh [[dynamic RAM]]. In most systems this is normally handled by the [[video display controller]] or external logic. This was implemented via a separate Refresh Counter (RC) register that held the currently updating page of memory. The feature is turned on by setting the most significant bit of the RC, bit 15, to 1. The following six bits, 14 through 9 are a rate, measured in terms of every 4th clock cycle. With a standard 4&nbsp;MHz clock, that allows the refresh to be called every 1 to 64&nbsp;microseconds. The remaining 8 bits select a row in memory to refresh.<ref name="abramovitz1981"/>{{rp|pages=6.5,6.28}}

The Z8000 has a [[segmented memory]] map, with a 7-bit "segment number" and a 16-bit offset. Both numbers are represented by pins on the Z8001, meaning that it can directly address a 23-bit memory, or 8&nbsp;MB.<ref name="abramovitz1981"/>{{rp|pages=6.19}} Instructions can only directly access a 16-bit offset. This allows the instruction format to be smaller; a system with direct access to a 23-bit address would need to read three bytes (24 bits) from memory for every address referred to in the code, thus requiring two reads on a 16-bit bus. With segments, the addresses need only a single 16-bit read which is then added to a segment number to produce the complete address. The segment number only needs to be updated when the data crosses the 16-bit/64&nbsp;KB boundaries.<ref name="abramovitz1981"/>{{rp|pages=6.3}}

Internally, addresses are all 32 bits: an upper 16-bit word with a leading 0 in bit 15, the 7-bit segment number, and then 8 zeros. This requires more memory to store, as each 23-bit address uses up 32 bits of register space, but allows the addresses to be cleanly stored in the 16-bit registers and can be more easily pushed and popped from the stack, which occurs in 16-bit words.<ref name="abramovitz1981"/>{{rp|pages=6.6}}

The optional 48-pin Z8010 [[memory management unit]] (MMU) expands the memory map to 16&nbsp;MB by translating the 23-bit address from the CPU to a 24-bit one. A Z8010 has 64 segment descriptor registers, each of which contains a 16-bit base physical address, an 8-bit limit, and an 8-bit set of attributes. When the CPU attempts to access a particular segment, a 7-bit value, the Z8010 uses the lower 6 bits of the segment number to select a segment descriptor register, checks the 16-bit offset in the segment against the limit value in that register and checks the permission bits in the attributes to see whether the access is allowed and, if the access is allowed, adds the base physical address to the segment offset to generate a physical address. This allows multiple programs to be spread out in physical RAM, each given its own space to work in while believing it is accessing the entire 8&nbsp;MB of RAM. The segments are variable length, expanding up to 64&nbsp;KB in order to allow the entire memory to be accessed from 64 segments. If more than 64 segments are needed, multiple Z8010s can be used, with the upper bit of the 7-bit segment number selecting which Z8010 is used.<ref name="mmu">{{cite journal |author-last=Fawcett |author-first=B. K. |date=1983 |title=A tutorial overview of the Z8003 and Z8004 microprocessors and the Z8010 and Z8015 memory management units |journal=Journal of Microcomputer Applications |volume=6 |issue=2 |pages=163–178 |doi=10.1016/0745-7138(83)90028-3 }}</ref><ref name="mmu-datasheet">{{cite book |url=http://www.bitsavers.org/components/zilog/z8000/1988_Zilog_Z8000_Family_Data_Book.pdf |title=Z8000 Family Data Book |pages=163–178 |publisher=Zilog |date=November 1988}}</ref> The Z8010 was not available at the time of launch, and was ultimately nine months to a year late.{{sfn|OHP_2010_Z8000|p=20}}

With the release of the Z8003/Z8004, the Z8015 was added to the lineup, adding [[paged memory]] support. The main difference is that the Z8015 breaks down the memory into 64 2&nbsp;KB blocks, whereas the Z8010 broke memory into 64 variable-sized blocks, up to 64&nbsp;KB each. Additionally, the Z8015 expands the segment number from 7 to 12 bits, and then using those as the most significant bits of the 23-bit overall address, overriding the upper bits of the original 16-bit offset. The advantage to this access scheme is that it is easy to read or write 2&nbsp;KB blocks to a [[hard drive]], so this pattern more closely matches what will ultimately happen on a [[page fault]].<ref name="mmu"/>

=== Example code ===
The following Z8000 assembly source code is for a subroutine named <code>MEMCPY</code> that copies a block of data words from one location to another. The data block is copied one word at a time, and the data movement and looping logic utilizes 16-bit operations. It demonstrates a variety of instructions but in practice it would not be coded this way as the Z8000 has a single instruction that will replace this entire subroutine: <code>LDIR</code>. The sample code will move one word every 34 cycles. Substituting the <code>LDIR</code> instruction will move a word in only 9 cycles.
<!--This was assembled by brain so it may contain errors. I realize two instructions and some cycles could be saved by using POP @R2,@R1 to move the data but that would obfuscate the example.-->
{|
|-valign="top"
|<syntaxhighlight lang="text">

 
 
 
 
 
 
 
 
 
 
 

 
 
 
 1000
 1000 93F4
 1002
 1002 2114
 1004 2F24
 1006 A911
 1008 A921
 100A F285
 100C
 100C 97F4
 100E 9E08
 1010
</syntaxhighlight>
|<syntaxhighlight lang="tasm">
 ; memcpy --
 ; Copy a block of memory from one location to another.
 ; This routine is the equivalent of
 ; LDIR @R2,@R1,R0 (LDIR @dst,@src,cnt)
 ;
 ; Entry registers
 ; R1 - Address of source data block
 ; R2 - Address of destination data block
 ; R0 - Number of words to copy
 ;
 ; Return registers
 ; R1 - First word after source data block
 ; R2 - First word after destination data block
 ; R0 - Zero
 
             ORG     1000h       ;Origin at 1000h
 MEMCPY:     PUSH    @R15,R4     ;Save temp register like LDIR
 
 LOOP:       LD      R4,@R1      ;Load source word
             LD      @R2,R4      ;save it
             INC     R1,#2       ;Bump source by 2 for words
             INC     R2,#2       ;Bump dest pointer by 2
             DJNZ    R0,LOOP     ;Bump count, loop if != 0
             
             POP     R4,@R15     ;Restore temp register
             RET
             END
</syntaxhighlight>
|}

===Other features===
One uncommon feature found on the Z8000, more commonly associated with [[minicomputer]]s, is direct support for [[vectored interrupt]]s. Interrupts are used by external devices to notify the processor that some condition has been met; a common use is to indicate that data from a slow process like reading a [[floppy disk]] is now available and the CPU can read the data into memory.

Normally on small machines, an [[interrupt]] causes special code to run that examines various status bits and memory locations to decide what device actually called the interrupt and why. In some designs, especially those intended for [[realtime computing]], an area of memory is set aside as a set of pointers, or vectors, to the code handling a particular device. The devices causing the interrupt then set some state, typically via pins on the CPU, to indicate a particular interrupt number, N. When the interrupt is called, the CPU immediately jumps through Nth entry in the table, avoiding any need to decode the interrupt. This can greatly speed up the interrupt servicing by avoiding having to run additional operations, while also simplifying the interrupt handling code.

In the Z8000, a new register supports vectors, the Program Status Area Pointer. This was similar to a memory address in a register, consisting of two 16-bit values with the upper 16 bits holding the segment number in its upper 8 bits. The lower 16 bits are then divided in half, the upper 8 bits containing an offset and the lower 8 bits zeroed. To call a particular vector, the external device presents the lower 8 bits (or 9 in some cases) on the address/data bus, and the complete vector address is constructed from the three values.<ref name="abramovitz1981"/>{{rp|pages=6.8}}

==Support chips==

===Zilog===
* Z8010: Memory management Unit<ref>{{cite web |url=http://www.bitsavers.org/components/zilog/z8000/z8000DataSheets/z8010_mmu.pdf |title=Z8010 Z8000 MMU Memory Management Unit Product Specification |publisher=Zilog |date=April 1985}}</ref>
* Z8016: Direct Memory Access Transfer Controller<ref>{{cite web |url=http://www.bitsavers.org/components/zilog/z8000/z8000DataSheets/z8016_dtc.pdf |title=Z8000 Z8016 Z-DTC Direct Memory Access Transfer Controller Product Specification |publisher=Zilog |date=April 1985}}</ref>
* Z8030: [[Zilog SCC|Serial Communications Controller]]<ref>{{cite web |url=http://www.bitsavers.org/components/zilog/z8000/z8000DataSheets/z8030_scc.pdf |title=Z8030 Z8000 Z-SCC Serial Communications Controller Product Specification |publisher=Zilog |date=April 1985}}</ref>
* Z8036: Counter/Timer and Parallel I/O Unit<ref>{{cite web |url=http://www.bitsavers.org/components/zilog/z8000/z8000DataSheets/z8036_cio.pdf |title=Z8036 Z8000 Z-CIO Counter/Timer and Parallel I/O Unit |publisher=Zilog |date=April 1985}}</ref>
* Z8090: Universal Peripheral Controller<ref>{{cite book |url=http://www.bitsavers.org/components/zilog/_dataBooks/1982_Zilog_Data_Book.pdf |title=1982/83 Data Book |chapter=Z8090 Z8000 Z-UPC Universal Peripheral Controller Product Specification |pages=313–332 |publisher=Zilog |date=1982}}</ref>
* Z8531: Clock Generator and Controller<ref>{{cite web |url=http://www.bitsavers.org/components/zilog/z8000/z8000DataSheets/z8581_clock.pdf |title=Z8581 Clock Generator and Controller Product Specification |publisher=Zilog |date=April 1985}}</ref>

===Sharp===
* LH8010/LH8010A: Z8010/Z8010A compatible Memory Management Unit<ref>{{Cite web |url=http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=339 |title=Sharp 1986 Semiconductor Data Book |accessdate=2024-01-01 |page=332-341}}</ref>
* LH8036/LH8036A: Z8036/Z8036A compatible Counter/Timer and Parallel I/O Unit<ref>{{Cite web |url=http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=363 |title=Sharp 1986 Semiconductor Data Book |accessdate=2024-01-01 |page=356-376}}</ref>
* LH8072: serial parallel combination controller with internal 128-byte FIFO<ref>{{Cite web |url=http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=420 |title=Sharp 1986 Semiconductor Data Book |accessdate=2024-01-01 |page=413-420}}</ref>
* LH8073: [[GPIB]] controller<ref>{{Cite web |url=http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=428 |title=Sharp 1986 Semiconductor Data Book |accessdate=2024-01-13 |page=421-422}}</ref>
* LH8090: Z8090 compatible Universal Peripheral Controller.<ref>{{Cite web |url=http://www.bitsavers.org/components/sharp/_dataBooks/1986_Sharp_MOS_Semiconductor_Data_Book.pdf#page=441 |title=Sharp 1986 Semiconductor Data Book |accessdate=2024-01-22 |page=434-450}}</ref>

==Z8000 CPU based systems==
In the early 1980s, the Zilog Z8000 CPU was popular for desktop-sized [[Unix]] machines. These low-cost Unix systems allowed small businesses to run a true multi-user system and share resources (disk, printers) before networking was common. They usually had only [[RS-232]] [[serial port]]s (4–16) and [[parallel port|parallel printer ports]] instead of built-in graphics, as was typical for servers of the time.

Z8000-based computer systems included Zilog's own System 8000 series, as well as other manufacturers: 
* 1980: C8002 made by [[Onyx Systems]] used the Z8002, ran [[Version 7 Unix]], had C, FORTRAN 77 and COBOL compilers available. It had eight serial ports for terminal connections, 1 QIC tape drive and cost ~$25k. The main processor offloaded the disk, tape, and serial I/O operations to a Z80 processor on a second board.<ref name="pcw198103_onyxc8002">{{ cite magazine | url=https://archive.org/details/PersonalComputerWorld1981-03/page/52/mode/2up | title=Onyx C8002 | magazine=Personal Computer World | last1=Eisenbach | first1=Sue | date=March 1981 | access-date=26 February 2023 | pages=52–53,55–57 }}</ref>
* 1981: Zilog Systems Z-Lab 8000 Programmer's Development System, available as a Model 20 system with 256&nbsp;KB of RAM and single 24&nbsp;MB hard drive, priced at $27,000, or a Model 30 system with 512&nbsp;KB of RAM and dual hard drives, priced at $33,950, ran the Zeus enhanced version of Unix from Zilog.<ref name="computerworld19810316_zilog">{{ cite magazine | url=https://archive.org/details/computerworld1511unse/page/50/mode/1up | title=Z8000 Development System Runs Under Unix | magazine=Computerworld | date=16 March 1981 | access-date=10 March 2023 | pages=50 }}</ref> Zilog followed up with the Series 8000, a multi-user business system that, like the Z-Lab 8000, was based on the 6&nbsp;MHz Z8001A with three Z8010A memory management units.<ref name="computerbusinessnews19810907_zilog">{{ cite magazine | url=https://archive.org/details/sim_micro-marketworld_1981-09-07_4_36/page/n11/mode/1up | title=Version of Z-Lab 8000 Handles Multiple Users | magazine=Computer Business News | date=7 September 1981 | access-date=13 March 2023 | pages=10 }}</ref>
* 1981-1982: Plexus Computers P/40 employed the Z8001<ref name="computerdesign198202_myers">{{ cite magazine | url=http://www.bitsavers.org/magazines/Computer_Design/Computer_Design_V21_N02_198202_A_Multiprocessor_Minicomputer_Designed_for_Unix.pdf | title=A Multiprocessor Minicomputer Designed for UNIX | magazine=Computer Design | last1=Myers | first1=Curtis | last2=Munsey | first2=Grant | date=February 1982 | access-date=16 February 2025 | pages=87–88,90,92,94,96 }}</ref> along with a number of peripheral controllers designed to maximise data transfer performance, claiming direct memory access throughput of up to 3&nbsp;MB per second. A "typical eight-user P/40 configuration" with 512&nbsp;KB of RAM and 72&nbsp;MB hard drive cost $49,500, with a Unix licence costing $5,000 extra.<ref name="computerworld19810928_plexus">{{ cite magazine | url=https://archive.org/details/computerworld1539unse/page/n4/mode/1up | title=New Firm Has Mini 'Custom-Made' for Unix | magazine=Computerworld | last1=Beeler | first1=Jeffry | date=28 September 1981 | access-date=10 March 2023 | pages=5 }}</ref> Plexus followed up with the P/25 in 1982, claiming similar performance to a PDP-11/70 system.<ref name="computerworld19820405_plexus">{{ cite magazine | url=https://archive.org/details/computerworld1614unse/page/69/mode/1up | title=Plexus Unveils 16-Bit Multiprocessor Mini | magazine=Computerworld | date=5 April 1982 | access-date=10 March 2023 | pages=69 }}</ref> A later Plexus model, the P/60, employed the Z8000 as an input/output controller but introduced the Motorola 68000 as the main CPU.<ref name="computerworld19831010_benetics">{{ cite magazine | url=https://archive.org/details/computerworld1741unse/page/77/mode/1up | title=Benetics Offers Micro-Based Turnkey System | magazine=Computerworld | date=10 October 1983 | access-date=10 March 2023 | pages=77 }}</ref> The Plexus P/35 retained this general architecture.<ref name="unixworld198504_plexus">{{ cite magazine | url=https://archive.org/details/Unix_World_Vol02_03.pdf/page/n85/mode/2up | title=The Plexus Challenge: Reviewing the P/35 | magazine=UNIX/WORLD | date=April 1983 | access-date=10 March 2023 | last1=Mackinlay | first1=Bruce | pages=84–90 }}</ref>
* 1982: BDC-600 from Bleasdale Computer Systems was offered in a configuration featuring the Z8000 running Xenix, providing 256&nbsp;KB of RAM, a floppy drive system and 10&nbsp;MB hard drive, supporting eight input/output ports. Based on the [[Multibus]] standard, other processor configurations were also announced involving boards utilising the 68000, Z80, 6809 and 8086.<ref name="practicalcomputing198205_bleasdale">{{ cite magazine | url=https://archive.org/details/practical-computing/PracticalComputing-1982-05/page/46/mode/1up | title=BDC-600 operates in the Unix tradition | magazine=Practical Computing | date=May 1982 | access-date=29 March 2024 | pages=46 }}</ref> Bleasdale later focused on the 68000 architecture with its BDC-680 series.<ref name="practicalcomputing198310_british">{{ cite magazine | url=https://archive.org/details/practical-computing/PracticalComputing-1983-10/page/3/mode/1up | title=Why British? | magazine=Practical Computing (British Micro Guide) | date=October 1983 | access-date=29 March 2024 }}</ref>{{rp|pages=8}}
* 1982: [[Olivetti M20]], a non-IBM-compatible PC that ran Olivetti PCOS, a derivative of COSMOS or CP/M 8000.<ref name="Kranenborg_2009">{{cite web |url=http://www.kranenborg.org/z8000/ |title=The Z8000 / Z80,000 / Z16C00 CPU homepage |access-date=2009-07-16 |author-last1=Kranenborg |author-first1=Jurjen |author-last2=Elvey |author-first2=Dwight K. |author-last3=Groessler |author-first3=Christian}}</ref>
* 1982-1983: C5002A, C8002A and Sundance-16 from Onyx Systems used the Z8001 and ran [[Unix System III]].<ref name="onyx_c5002a">{{ cite book | url=https://archive.org/details/bitsavers_onyxbrochuProductDescriptionFeb83_2404879/mode/2up | title=C5002A, C8002A Series Product Description | publisher=Onyx Systems Inc. | date=February 1983 | access-date=3 March 2023 }}</ref><ref name="onyx_sundance16">{{ cite book | url=https://archive.org/details/bitsavers_onyxbrochuoductDescriptionOct82_2791970/mode/2up | title=Sundance-16 Product Description | publisher=Onyx Systems Inc. | date=October 1982 | access-date=2 March 2023 }}</ref>
* 1983: Zilog Systems 8000 Series Two featured a faster 11.1&nbsp;MHz Z8001B processor with 32&nbsp;KB of cache memory, available in three models with 512&nbsp;KB of RAM expandable to 2&nbsp;MB in the base model and 4&nbsp;MB in the other models, with prices for minimal configurations ranging from $19,950 to $29,950. These systems ran Unix System III.<ref name="computerworld198409010_zilog">{{ cite magazine | url=https://archive.org/details/sim_computerworld_1984-09-10_18_37/page/n148/mode/1up | title=Zilog introduces Unix-based multiuser computer systems | magazine=Computerworld | last1=Sullivan | first1=Kathleen | date=10 September 1984 | access-date=10 March 2023 | pages=101 }}</ref>
* 1983: Exxon Office Systems 500 series and 8400 series.<ref name="computerworld19840815_exxon">{{ cite magazine | url=https://archive.org/details/sim_computerworld_1984-08-15_18_33a/page/21/mode/1up | title=The Future – Or the Shock? | magazine=Computerworld | last1=Rifkin | first1=Glenn | date=15 August 1984 | access-date=10 March 2023 | pages=21–22,24 }}</ref><ref name="computerworld19830228_exxon">{{ cite magazine | url=https://archive.org/details/computerworld179unse/mode/2up | title=HP, DG Sign Pacts With PBX Makers | magazine=Computerworld | last1=Hoard | first1=Bruce | date=28 February 1983 | access-date=10 March 2023 | pages=1,14 }}</ref>
* 1980-1986: [[Olivetti]] Linea 1 S1000, S6000, M30, M40, M50, M60, M70. These minicomputers from Olivetti all ran BCOS/COSMOS.<ref name="Kranenborg_2009"/>
* 1985: the cancelled [[Commodore 900]] computer project
* 1986: [[VEB Robotron]] produced the [[A 5120.16]] based on the East German U8000 clone of the Z8000.
* 1987–1989: the East German EAW ([[Elektro-Apparate-Werke]]) produced the Workstation/Multiuser System [[P8000]] based on the East German U8000 clone of the Z8000.<ref name="Sun">{{cite web |url=http://articles.sun-sentinel.com/1990-07-01/news/9001160696_1_east-west-german-east-berlin-workers |archive-url=https://web.archive.org/web/20150705062948/http://articles.sun-sentinel.com/1990-07-01/news/9001160696_1_east-west-german-east-berlin-workers |url-status=dead |archive-date=5 July 2015 |title=E. German Businesses See Tough Times After Merger |access-date=2015-07-03 |publisher=Sun Sentinel}}</ref>

{{anchor|ZEUS}}The '''Zilog S8000''' computer came out with a version of Unix called ZEUS (Zilog Enhanced Unix System). ZEUS was a port of Unix Version 7 and included what were referred to as 'the Berkeley Enhancements'. ZEUS included a version of [[COBOL]] called RM/COBOL (Ryan McFarland COBOL). The availability of RM/COBOL allowed many commercial applications to be quickly ported to the S8000 computer although this did not help its long-term success. The S8000 did find some success with the [[Internal Revenue Service|IRS]] and tax preparers in United States, who used the model for processing of electronically filed tax returns.<ref name="eTax_2012">{{cite web |url=http://www.efile.com/efile-electronic-tax-filing-history/ |title=efile History - Electronic Tax Filing in the United States |access-date=2012-12-13}}</ref>

The Z8000 featured in Steve Ciarcia's ''Trump Card'' project for his Circuit Cellar column in [[Byte magazine]], providing an expansion card with the Z8001 processor and 512&nbsp;KB of RAM suitable for use with an IBM-compatible PC.<ref name="byte198405_ciarcia">{{ cite magazine | url=https://archive.org/details/byte-magazine-1984-05/page/n41/mode/2up | title=Trump Card Part 1: Hardware | magazine=Byte | last1=Ciarcia | first1=Steve | date=May 1984 | access-date=22 March 2023 | pages=40–52,54–55 }}</ref> Compilers for BASIC and C were supplied with the board, along with an assembler and a Z80 emulator that could run programs written for CP/M-80. It was envisaged that Unix would also be made available for the Trump Card.<ref name="byte198406_ciarcia">{{ cite magazine | url=https://archive.org/details/byte-magazine-1984-06/page/n112/mode/1up | title=Trump Card Part 2: Software | magazine=Byte | last1=Ciarcia | first1=Steve | date=June 1984 | access-date=22 March 2023 | pages=115–122 }}</ref>

Despite a somewhat positive reception as "a reasonably fast supermicro with generally good performance for the price", the 16-bit architectural limitations of the Z8000, with segment handling required to access more than 64&nbsp;KB in a process, led to questions about the longevity of the Series 8000 products as 32-bit processor architectures from Motorola and National Semiconductor became more widely adopted.<ref name="unixworld198511_zilog">{{ cite magazine | url=https://archive.org/details/Unix_World_Vol02_10.pdf/page/n55/mode/2up | title=The Zilog System 8000 | magazine=UNIX/WORLD | date=November 1985 | access-date=10 March 2023 | last1=Mackinlay | first1=Bruce | pages=56–57,59–60,64,66–68 }}</ref> Zilog Systems eventually adopted AT&T's 32-bit [[Bellmac 32|WE32100]] processor, introducing it in a new product, the System 8000/32, alongside 32-bit upgrades to its existing System 8000 Series 2 models. This enabled the introduction of Unix System V on Zilog Systems' products.<ref name="computerworld19851118_zilog">{{ cite magazine | url=https://archive.org/details/computerworld1946unse/page/2/mode/1up | title=Zilog Unix-based system bows | magazine=Computerworld | date=18 November 1985 | access-date=10 March 2023 | last1=McEnaney | first1=Maura | pages=2 }}</ref>

The adoption by Zilog's Systems Division of the WE32100, in preference to the continued use of products from Zilog's Component Division, was driven by diverging requirements. Zilog sought to introduce its 32-bit successor to the Z8000, the Z80000, to build on successful adoption of the 16-bit product in military and graphical applications, whereas its Systems Division prioritised Unix support and commercial applications. The conclusion was reached to adopt the WE32100 as "the premier UNIX chip".<ref name="unixreview198601_zilog">{{ cite magazine | url=https://archive.org/details/sim_unix-review_1986-01_4_1/page/91/mode/1up | title=Zilog: Synergic but Separate | magazine=UNIX Review | date=January 1986 | access-date=10 March 2023 | pages=91–92 }}</ref> Zilog subsequently announced an agreement to manufacture the WE32100 chipset for a five year period, being the first alternative source of these products.<ref name="computerworld19860519_zilog">{{ cite magazine | url=https://archive.org/details/computerworld2020unse/page/125/mode/1up | title=Zilog to make AT&T chip | magazine=Computerworld | date=19 May 1986 | access-date=10 March 2023 | pages=125 }}</ref>

There was a Z8000 version of the [[Xenix]] Operating System.<ref name="Bezroukov_2008">{{cite web |url=http://www.softpanorama.org/People/Torvalds/Finland_period/xenix_microsoft_shortlived_love_affair_with_unix.shtml |title=XENIX—Microsoft's Short-lived Love Affair with Unix |access-date=2009-07-16 |author-last=Bezroukov |author-first=Nikolai |author-link=Nikolai Bezroukov |date=2008-11-15 |publisher=Softpanorama}}</ref> In 1982, Digital Research and Zilog announced an agreement to make CP/M available for the Z8000.<ref name="computerworld19821101_cpm">{{ cite magazine | url=https://archive.org/details/computerworld1644unse/page/82/mode/1up | title=Supershorts | magazine=Computerworld | date=1 November 1982 | access-date=10 March 2023 | pages=82 }}</ref>

[[Namco]] used the Z8000 series in its ''[[Pole Position]]'' and ''[[Pole Position II]]'' arcade games. The machines used two Z8002's, the 64&nbsp;KB versions of the Z8000.

In one instance, the Z8001 was used to implement a capability-based architecture, employing the segment number in the addressing model of the Z8001 to indicate a capability register in a virtual processor. Such virtual processors were provided through the augmentation of the Z8001 with an "intelligent memory device", this providing memory management and context switching facilities, with additional capability-related instructions being supported through emulation.<ref name="ieeemicro198706_capability">{{ cite magazine | url=https://archive.org/details/ieee_micro_v7n3_june_87/page/n36/mode/1up | title=The Architecture of a Capability-Based Microprocessor System | magazine=[[IEEE Micro]] | volume=7 | issue=3 | date=June 1987 | access-date=8 April 2023 | last1=Corsini | first1=Paolo | last2=Lopriore | first2=Lanfranco | pages=35–51 | doi=10.1109/MM.1987.304982 }}</ref>

The reported inclusion of the device within military designs<ref name="TE_2009">{{cite encyclopedia |url=http://www.techweb.com/encyclopedia/defineterm.jhtml?term=Z8000 |archive-url=https://web.archive.org/web/20110611130711/http://www.techweb.com/encyclopedia/defineterm.jhtml?term=Z8000 |url-status=dead |archive-date=11 June 2011 |title=Z8000 |access-date=2009-07-16 |encyclopedia=TechEncyclopedia |publisher=TechWeb}}</ref> perhaps provides an explanation for the continued survival of the Z8000, in the shape of the Zilog Z16C01/02 CPUs. Also, the [[Central Air Data Computer|Standard Central Air Data Computer (SCADC)]] was using the Z8002.<ref name="GEC">{{cite book |title=Standard Central Air Data Computer |date=1985 |publisher=GEC Avionics |url=http://rochesteravionicarchives.co.uk/img/catalog/ZZ_1376744342_DDBR0298%20%28O&A-1b%29.pdf}}</ref> However, the end of life notice from Zilog was sent in 2012.<ref name="ZAC12">{{cite web |url=http://media.digikey.com/pdf/PCNs/Zilog/zac12-0011.pdf |title=Z16C0110PSG and Z16C0210PSG End of Life (EOL) Notification |access-date=2016-07-17}}</ref>

== Limited success ==
{{original research|section|date=February 2023}}

While the Z8000 did see some use in the early 1980s, it was passed over for other designs relatively quickly.<ref name="chm2006_faggin">{{cite interview | url=http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf | title=Oral History of Federico Faggin | author-last=Hendrie | author-first=Gardner | date=2006 | publisher=Computer History Museum | access-date=2017-01-24 }}</ref>

[[Federico Faggin]], then CEO of Zilog, later suggested this was due to Zilog's financing arrangement with [[Exxon]]'s venture capital arm, Exxon Enterprises. Enterprises had made a number of investments in the computer field, and by the early 1980s was positioning itself as a competitor to [[IBM]] in the large system space. Faggin suggested that IBM thus saw Zilog as a competitor, and refused to consider the Z8000 as a result.<ref name="chm2006_faggin"/>

However, Faggin did concede that the segmented architecture of the Z8000 was a disadvantage for emerging "graphics-based applications", where systems such as the Apple Macintosh needed to readily access more than 64&nbsp;KB of memory in a single address space. The longer than anticipated process of bringing the product to market was also acknowledged as having contributed to its lack of adoption, Faggin noting that "being first and having the strongest marketing and the strongest momentum", as Intel had found itself with the 8086, would have been the only remaining route to success for a product of this kind.<ref name="panel_z8000">{{cite interview | first1=Federico | last1=Faggin | first2=Bernard | last2=Peuto | first3=Masatoshi | last3=Shima | first4=Ralph | last4=Ungermann | title=Oral History Panel on the Development and Promotion of the Zilog Z8000 Microprocessor | url=https://archive.computerhistory.org/resources/access/text/2015/06/102658075-05-01-acc.pdf | date=27 April 2007 | ref=CITEREFOHP_2010_Z8000 }}</ref>

An examination of the choices available to designers in the early 1980s suggests there are several prosaic reasons the Z8000 was not more popular:

Comparing [[assembly language]] versions of the [[Byte Sieve]], one sees that the 5.5&nbsp;MHz&nbsp;Z8000's 1.1 seconds is impressive when compared to the 8-bit designs it replaced, including Zilog's 4&nbsp;MHz Z80 at 6.8 seconds, and the popular 1&nbsp;MHz [[MOS 6502]] at 13.9. Even the newer 1&nbsp;MHz [[Motorola 6809]] was much slower, at 5.1 seconds.<ref name="Gilbreath">{{cite magazine |title=Eratosthenes Revisited: Once More through the Sieve |first1=Jim |last1=Gilbreath |first2=Gary |last2=Gilbreath |magazine=[[Byte (magazine)|Byte]] |date=January 1983 |pages=283–325 |url=https://archive.org/details/byte-magazine-1983-01/page/n291}}</ref> It also fares well against the 8&nbsp;MHz [[Intel 8086]] which turned in a time of 1.9 seconds, or the less expensive 5&nbsp;MHz [[Intel 8088]] at 4 seconds.<ref name="Gilbreath" />

While the Intel processors were easily outperformed by the Z8001, they were packaged in 40-pin DIPs, which made them less expensive to implement than the 48-pin Z8001. The Z8002 also used a 40-pin package, but had a 16-bit address bus that could only access 64&nbsp;KB of RAM, whereas the Intel processors had a 20-bit bus that could access 1 MB of RAM. Internally, the 23-bit addresses of the Z8000 were also more complex to process than Intel's simpler system using 16-bit base addresses and separate segment registers. For those looking for a low-cost option able to access (what was then) large amounts of memory, the Intel designs were competitive and available over a year earlier.<ref name="Gilbreath" />{{better source |date=June 2023| reason=This benchmarking article does not cover package types, bus widths, address sizes or any of this kind of architectural discussion. }}

For those looking for pure performance, the Z8000 was the fastest CPU available in early 1979. But this was true only for a period of a few months. The 16/32-bit 8&nbsp;MHz [[Motorola 68000]] came to market later the same year and turns in a time of 0.49 seconds on the same Sieve test, over twice as fast as the Z8000.<ref name="Gilbreath" /> Although it used an even larger 64-pin DIP layout, for those willing to move to more than 40 pins this was a small price to pay for what was by far the fastest processor of its era. Its 32-bit instructions and registers, combined with a 24-bit address bus with flat 16&nbsp;MB addressing, also made it much more attractive to designers, something Faggin admits to.<ref name="chm2006_faggin"/>

To add to its problems, when the Z8000 was first released it contained a number of bugs. This was due to its complex instruction decoder, which, unlike most processors of the era, did not use [[microcode]] and was dependent on logic implemented directly in the CPU. This allowed the design to eliminate the microcode storage and the associated decoding logic, which reduced the transistor count to 17,500.<ref>{{cite web |url=http://www.cpushack.com/CPU/cpu3.html#Sec3Part3 |title= Zilog Z-8000, another direct competitor |website= Great Microprocessors of the Past and Present |date= December 2003 |first=John |last=Bayko}}</ref> In contrast, the contemporary [[Intel 8088]] used 29,000 transistors,<ref>{{cite web |title=Chip Hall of Fame: Intel 8088 Microprocessor |url=https://spectrum.ieee.org/chip-hall-of-fame-intel-8088-microprocessor |website=[[IEEE Spectrum]] |publisher=[[Institute of Electrical and Electronics Engineers]] |access-date=19 June 2020 |date=30 June 2017}}</ref> while the [[Motorola 68000]] of a few months later used 68,000.<ref>{{cite news |title=Chip Hall of Fame: Motorola MC68000 Microprocessor |url=https://spectrum.ieee.org/chip-hall-of-fame-motorola-mc68000-microprocessor |website=[[IEEE Spectrum]] |publisher=[[Institute of Electrical and Electronics Engineers]] |access-date=19 June 2019 |date=30 June 2017}}</ref>

==Second sources==
Several third parties manufactured the Z8000 including [[AMD]],<ref name="microcomputing198205_sixteen">{{ cite magazine | url=https://archive.org/details/198205KilobaudMicrocomputing/page/n35/mode/2up | title=Sweet Sixteen – Micros Come of Age | magazine=Microcomputing | last1=Nelson | first1=Harold | date=May 1982 | access-date=10 March 2023 | pages=36–38 }}</ref> [[STMicroelectronics|SGS-Ates]], [[Toshiba]] and [[Sharp Corporation|Sharp]].<ref name="digital history zilog z8000">{{cite web |url=https://www.old-computers.com/history/detail.asp?n=52&t=3 |title=Zilog Z8000 |date=April 1979 |access-date=2009-07-16 |work=Digital History: Time Line |publisher=old-computers.com}}</ref>
<gallery caption="Zilog Z8000 [[second source]]s" mode="packed">
AMD Z8002APC 1.jpg|[[AMD]] Z8002APC
MME UB8001C 1.jpg|[[Kombinat Mikroelektronik Erfurt|VEB Mikroelektronik "Karl Marx" Erfurt (MME)]] UB8001C
Sharp LH8002P 1.jpg|[[Sharp Corporation|Sharp]] LH8002P
</gallery>

==Notes==
{{notelist}}

==References==
===Citations===
{{Reflist}}

===Bibliography===

* {{cite journal |author-last=Fawcett |author-first=B. K. |date=1983 |title=A tutorial overview of the Z8003 and Z8004 microprocessors and the Z8010 and Z8015 memory management units |journal=Journal of Microcomputer Applications |volume=6 |issue=2 |pages=163–178 |doi=10.1016/0745-7138(83)90028-3 |ref=CITEREFmmu }}
* {{cite web |url=http://www.granneman.com/techinfo/background/history/ |title=Computing History 1968–Present |access-date=2009-07-16 |author-last=Granneman |author-first=Scott |author-link=Scott Granneman |ref=Granneman_2009}}
* {{cite book |url=http://www.bitsavers.org/components/zilog/z8000/1988_Zilog_Z8000_Family_Data_Book.pdf |title=Z8000 Family Data Book |pages=163–178 |publisher=Zilog |date=November 1988 |ref=mmu-datasheet}}
* {{cite web |url=http://www.kranenborg.org/z8000/ |title=The Z8000 / Z80,000 / Z16C00 CPU homepage |access-date=2009-07-16 |author-last1=Kranenborg |author-first1=Jurjen |author-last2=Elvey |author-first2=Dwight K. |author-last3=Groessler |author-first3=Christian |ref=Kranenborg_2009}}
* {{cite web |url=http://articles.sun-sentinel.com/1990-07-01/news/9001160696_1_east-west-german-east-berlin-workers |archive-url=https://web.archive.org/web/20150705062948/http://articles.sun-sentinel.com/1990-07-01/news/9001160696_1_east-west-german-east-berlin-workers |url-status=dead |archive-date=5 July 2015 |title=E. German Businesses See Tough Times After Merger |access-date=2015-07-03 |publisher=Sun Sentinel |ref=Sun}}
* {{cite web |url=http://www.efile.com/efile-electronic-tax-filing-history/ |title=efile History - Electronic Tax Filing in the United States |access-date=2012-12-13 |ref=eTax_2012}}
* {{cite web |url=http://www.softpanorama.org/People/Torvalds/Finland_period/xenix_microsoft_shortlived_love_affair_with_unix.shtml |title=XENIX—Microsoft's Short-lived Love Affair with Unix |access-date=2009-07-16 |author-last=Bezroukov |author-first=Nikolai |author-link=Nikolai Bezroukov |date=2008-11-15 |publisher=Softpanorama |ref=Bezroukov_2008}}
* {{cite encyclopedia |url=http://www.techweb.com/encyclopedia/defineterm.jhtml?term=Z8000 |archive-url=https://web.archive.org/web/20110611130711/http://www.techweb.com/encyclopedia/defineterm.jhtml?term=Z8000 |url-status=dead |archive-date=11 June 2011 |title=Z8000 |access-date=2009-07-16 |encyclopedia=TechEncyclopedia |publisher=TechWeb |ref=TE_2009}}
* {{cite book |title=Standard Central Air Data Computer |date=1985 |publisher=GEC Avionics |url=http://rochesteravionicarchives.co.uk/img/catalog/ZZ_1376744342_DDBR0298%20%28O&A-1b%29.pdf |ref=GEC}}
* {{cite web |url=http://media.digikey.com/pdf/PCNs/Zilog/zac12-0011.pdf |title=Z16C0110PSG and Z16C0210PSG End of Life (EOL) Notification |access-date=2016-07-17 |ref=CITEREFZAC12}}
* {{cite web |url=https://www.old-computers.com/history/detail.asp?n=52&t=3 |title=Zilog Z8000 |date=April 1979 |access-date=2009-07-16 |work=Digital History: Time Line |publisher=old-computers.com |ref=digital history zilog z8000}}
* {{cite interview
 |first=Michael |last=Slater
|title=Development and Promotion of the Zilog Z8000 Microprocessor
|date=27 April 2007
|url=https://archive.computerhistory.org/resources/access/text/2015/06/102658075-05-01-acc.pdf
}}

==Further reading==
* {{cite book |title=Zilog Z8000 CPU Technical Manual |url=http://www.bitsavers.org/components/zilog/z8000/Z8000Tech.pdf |access-date=2009-07-16 |publisher=[[Zilog]] |location=[[San Jose, California]]}}
* {{cite book |title=Zilog Z8000 CPU User's Reference Manual |url=http://www.bitsavers.org/components/zilog/z8000/Z8000_CPUrefMan_1982.pdf |access-date=2009-07-16 |date=1982 |publisher=[[Zilog]] |location=[[San Jose, California]]}}
* {{cite web |url=http://www.zilog.com/docs/serial/cps95scc01.pdf |title=Z16C01/Z16C02 Product Specification |access-date=2009-07-15 |date=1995 |publisher=[[Zilog]] |location   =[[San Jose, California]]}}
* Levanthal, Lance. ''Z8000 Assembly Language Programming'', Osborne/McGraw-Hill, 1980.
* {{cite web |url=http://pofo.de/S8000/ |title=poto.de: Zilog S8000 |access-date=2009-07-16 |author-last=Lehmann |author-first=Oliver}}
* {{cite web |url=http://www.bitsavers.org/components/zilog/z8000/Fawcett_Z8000_Design_Handbook_1982.pdf |title=The Z8000 microprocessor: a design handbook |date=1982 |publisher=Englewood Cliffs, N.J.: Prentice-Hall |access-date=2013-03-06 |author-last=Fawcett |author-first=Bradly K.}}

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[[Category:Computer-related introductions in 1979]]
[[Category:Zilog microprocessors]]
[[Category:Japanese inventions]]
[[Category:16-bit microprocessors]]