View source for DDR3 SDRAM

{{short description|Third generation of double-data-rate synchronous dynamic random-access memory}}
{{about|the computer main memory|the graphics memory|GDDR3|the mobile memory|LPDDR3|the video game|Dance Dance Revolution 3rdMix}}

{{Infobox memory
| abbr       = DDR3 SDRAM
| name       = Double Data Rate 3 Synchronous Dynamic Random-Access Memory
| image      = File:2013 Transcend TS512MLK72V6N-(straightened).jpg
| caption    = 4 GB PC3-12800 ECC DDR3 DIMM
| developer  = [[JEDEC]]
| type       = [[Synchronous dynamic random-access memory]] (SDRAM)
| generation = 3rd generation
| release    = {{Start date and age|2007}}
| standards  = {{Unbulleted list|DDR3-800 (PC3-6400)|DDR3-1066 (PC3-8500)|DDR3-1333 (PC3-10600)|DDR3-1600 (PC3-12800)|DDR3-1866 (PC3-14900)|DDR3-2133 (PC3-17000)}}
| clock_rate = {{Nowrap|400–1066 MHz}}
| cycle_time = 
| prefetch   = 
| bus_clock_rate = 
| transfer_rate  = 
| bandwidth = 
| voltage   = {{Nowrap| Reference 1.5 V}}, {{Nowrap| 1.35V (DDR3L)}}
| predecessor = [[DDR2 SDRAM]] (2003)
| successor = [[DDR4 SDRAM]] (2014)
}}
'''Double Data Rate 3 Synchronous Dynamic Random-Access Memory''' ('''DDR3 SDRAM''') is a type of [[synchronous dynamic random-access memory]] (SDRAM) with a high [[Bandwidth (computing)|bandwidth]] ("[[double data rate]]") interface, and has been in use since 2007.  It is the higher-speed successor to [[DDR SDRAM|DDR]] and [[DDR2 SDRAM|DDR2]] and predecessor to [[DDR4 SDRAM|DDR4]] synchronous dynamic random-access memory (SDRAM) chips.  DDR3 SDRAM is neither [[Forward compatibility|forward]] nor [[Backward compatibility|backward compatible]] with any earlier type of [[random-access memory]] (RAM) because of different signaling voltages, timings, and other factors.

DDR3 is a DRAM interface specification. The actual DRAM arrays that store the data are similar to earlier types, with similar performance. The primary benefit of DDR3 SDRAM over its immediate predecessor DDR2 SDRAM, is its ability to transfer data at twice the rate (eight times the speed of its internal memory arrays), enabling higher bandwidth or peak data rates.

The DDR3 standard permits DRAM chip capacities of up to 8 [[gigabit]]s (Gbit) (so 1 gigabyte by DRAM chip), and up to four [[memory rank|ranks]] of 64 Gbit each for a total maximum of 16&nbsp;[[gigabyte]]s (GB) per DDR3 DIMM. Because of a hardware limitation not fixed until Ivy Bridge-E in 2013, most older Intel CPUs only support up to 4-Gbit chips for 8&nbsp;GB DIMMs (Intel's Core 2 DDR3 chipsets only support up to 2 Gbit). All AMD CPUs correctly support the full specification for 16&nbsp;GB DDR3 DIMMs.<ref>{{Cite web |url=http://www.anandtech.com/show/7742/im-intelligent-memory-to-release-16gb-unregistered-ddr3-modules |title=I'M Intelligent Memory to release 16GB Unregistered DDR3 Modules |date=2014-02-11 |first=Ian |last=Cutress |website=anandtech.com |access-date=2015-04-20}}</ref> Intel, also supports 16 GB DIMMs, from Broadwell (also named as "AMD Only" memory, because of using 11-bit addressing).

== History ==
In February 2005, [[Samsung]] introduced the first prototype DDR3 memory chip. Samsung played a major role in the development and standardisation of DDR3.<ref name="phys"/><ref name="samsung2000s">{{cite web |title=Our Proud Heritage from 2000 to 2009 |url=https://www.samsung.com/semiconductor/about-us/history-03/ |website=[[Samsung Semiconductor]] |publisher=[[Samsung]] |access-date=25 June 2019}}</ref> In May 2005, Desi Rhoden, chairman of the [[JEDEC]] committee, stated that DDR3 had been under development for "about 3 years".<ref name="digitimes_2005">{{cite web |url=http://www.digitimes.com/news/a20050530PR201.html |archive-url=https://web.archive.org/web/20130413141103/http://www.digitimes.com/news/a20050530PR201.html |title=JEDEC: Memory standards on the way |first=Vyacheslav |last=Sobolev |website=DigiTimes.com |date=2005-05-31 |access-date=2011-04-28 |quote=''JEDEC is already well along in the development of the DDR3 standard, and we have been working on it for about three years now.... Following historical models, you could reasonably expect the same three-year transition to a new technology that you have seen for the last several generations of standard memory'' |url-status=dead |archive-date=April 13, 2013 }}</ref>

DDR3 was officially launched in 2007, but sales were not expected to overtake DDR2 until the end of 2009 or possibly early 2010, according to Intel strategist Carlos Weissenberg, speaking during the early part of their roll-out in August 2008.<ref>{{cite web|url=http://www.pcpro.co.uk/news/220257/idf-ddr3-wont-catch-up-with-ddr2-during-2009.html|title=IDF: "DDR3 won't catch up with DDR2 during 2009"|date=19 August 2008|publisher=pcpro.co.uk|access-date=2009-06-17|archive-url=https://web.archive.org/web/20090402160556/http://www.pcpro.co.uk/news/220257/idf-ddr3-wont-catch-up-with-ddr2-during-2009.html|archive-date=2009-04-02|url-status=dead}}</ref> (The same timescale for market penetration had been stated by [[Marketing Intelligence|market intelligence]] company DRAMeXchange over a year earlier in April 2007,<ref>{{cite web|url=http://www.extremetech.com/article2/0,2845,2115031,00.asp|title=DDR3 Memory Won't Be Mainstream Until 2009|last=Bryan|first=Gardiner|date=April 17, 2007|website=ExtremeTech.com|access-date=2009-06-17|archive-date=2008-05-16|archive-url=https://web.archive.org/web/20080516094258/http://www.extremetech.com/article2/0,2845,2115031,00.asp|url-status=dead}}</ref> and by Desi Rhoden in 2005.<ref name="digitimes_2005" />) The primary driving force behind the increased usage of DDR3 has been new [[Core i7]] processors from Intel and [[Phenom II]] processors from AMD, both of which have internal memory controllers: the former requires DDR3, the latter recommends it. [[International Data Corporation|IDC]] stated in January 2009 that DDR3 sales would account for 29% of the total DRAM units sold in 2009, rising to 72% by 2011.<ref name="50nm">{{cite news|url=http://www.maximumpc.com/article/news/new_50nm_process_will_make_ddr3_faster_and_cheaper_this_year|title=New 50nm Process Will Make DDR3 Faster and Cheaper This Year|last=Salisbury|first=Andy|date=2009-01-20|newspaper=Pcgamer|access-date=2009-06-17}}</ref>

=== Successor ===
{{Main|DDR4 SDRAM}}

In September 2012, '''JEDEC''' released the final specification of DDR4.<ref>{{cite web|url=http://www.jedec.org/news/pressreleases/jedec-announces-publication-ddr4-standard|title=JEDEC Announces Publication of DDR4 Standard – JEDEC|publisher=JEDEC|access-date=12 October 2014}}</ref> The primary benefits of DDR4 compared to DDR3 include a higher standardized range of [[clock frequency|clock frequencies]] and [[Transfer (computing)|data transfer rates]]<ref name="xbit">{{cite web|url=http://www.xbitlabs.com/news/memory/display/20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report.html|title=Next-Generation DDR4 Memory to Reach 4.266GHz – Report|date=August 16, 2010|website=XbitLabs.com|access-date=2011-01-03|first=Anton|last=Shilov|url-status=dead|archive-url=https://web.archive.org/web/20101219085440/http://www.xbitlabs.com/news/memory/display/20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report.html|archive-date=December 19, 2010}}</ref> and significantly lower [[voltage]].

== Specification ==
=== Overview ===
{{Multiple image
| direction = vertical
| header    = Physical comparison of [[DDR SDRAM|DDR]], [[DDR2 SDRAM|DDR2]], and DDR3 [[Synchronous dynamic random-access memory|SDRAM]]
| image1    = Desktop DDR Memory Comparison.svg
| image2    = Laptop SODIMM DDR Memory Comparison V2.svg
| alt1      = Three long green circuit boards, identical in size, but each with a notch in a different location
| alt2      = Three short green circuit boards, identical in size, but each with a notch in a different location
| caption1  = Desktop PCs (DIMM)
| caption2  = Notebook and convertible PCs (SO-DIMM)
}}

Compared to DDR2 memory, DDR3 memory uses less power. Some manufacturers further propose using [[Multigate device|"dual-gate" transistors]] to reduce [[Leakage (electronics)|leakage]] of current.<ref>{{citation |last=McCloskey |first=Alan |title=Research: DDR FAQ |url=http://www.ocmodshop.com/ocmodshop.aspx?a=868 |access-date=2007-10-18 |archive-url=https://web.archive.org/web/20071112151558/http://www.ocmodshop.com/ocmodshop.aspx?a=868 |archive-date=2007-11-12 |url-status=dead }}</ref>

According to [[JEDEC]],<ref name="JESD79-3F">{{Cite web| url=http://www.jedec.org/standards-documents/docs/jesd-79-3d| title=DDR3 SDRAM standard (revision F)| publisher=JEDEC| date=July 2012| access-date=2015-07-05}}</ref>{{rp|111}} 1.575 volts should be considered the absolute maximum when memory stability is the foremost consideration, such as in servers or other mission-critical devices. In addition, JEDEC states that memory modules must withstand up to 1.80 volts{{efn|Prior to revision F, the standard stated that 1.975 V was the absolute maximum DC rating.<ref name="JESD79-3E">{{Cite web|url=http://www.jedec.org/sites/default/files/docs/JESD79-3E.pdf| title=DDR3 SDRAM standard (revision E)| publisher=JEDEC| date=July 2010| access-date=2015-07-05}}</ref>}} before incurring permanent damage, although they are not required to function correctly at that level.<ref name="JESD79-3F" />{{Rp|109}}

Another benefit is its [[prefetch buffer]], which is 8-burst-deep. In contrast, the prefetch buffer of DDR2 is 4-burst-deep, and the prefetch buffer of DDR is 2-burst-deep. This advantage is an enabling technology in DDR3's transfer speed.

DDR3 modules can transfer data at a rate of 800–2133&nbsp;[[Transfer (computing)|MT]]/s using [[Double data rate|both rising and falling edges]] of a 400–1066&nbsp;MHz I/O [[Clock signal|clock]]. This is twice DDR2's data transfer rates (400–1066&nbsp;MT/s using a 200–533&nbsp;MHz I/O clock) and four times the rate of DDR (200–400&nbsp;MT/s using a 100–200&nbsp;MHz I/O clock).  High-performance graphics was an initial driver of such bandwidth requirements, where high bandwidth data transfer between [[framebuffer]]s is required.

Because the [[hertz]] is a measure of ''cycles'' per second, and no signal cycles more often than every other transfer, describing the transfer rate in units of MHz is technically incorrect, although very common.  It is also misleading because various [[memory timings]] are given in units of clock cycles, which are half the speed of data transfers.

DDR3 does use the same electric signaling standard as DDR and DDR2, [[Stub Series Terminated Logic]], albeit at different timings and voltages. Specifically, DDR3 uses SSTL_15.<ref>{{cite web|first=Jaci|last=Chang|title=Design Considerations for the DDR3 Memory Sub-System|publisher=Jedex|date=2004|page=4|url=http://www.jedex.org/images/pdf/samsung%20-%20jaci_chang.pdf|url-status=dead|archive-url=https://web.archive.org/web/20120724110727/http://www.jedex.org/images/pdf/samsung%20-%20jaci_chang.pdf|archive-date=2012-07-24|access-date=2020-08-12}}</ref>

In February 2005, [[Samsung]] demonstrated the first DDR3 memory prototype, with a capacity of 512{{nbsp}}[[Megabit|Mb]] and a bandwidth of 1.066{{nbsp}}[[Gbps]].<ref name="phys">{{cite news |title=Samsung Demonstrates World's First DDR 3 Memory Prototype |url=https://phys.org/news/2005-02-samsung-world-ddr-memory-prototype.html |access-date=23 June 2019 |work=[[Phys.org]] |date=17 February 2005}}</ref> Products in the form of motherboards appeared on the market in June 2007<ref>{{cite web|url=http://www.tomshardware.com/2007/06/05/pipe_dreams_six_p35-ddr3_motherboards_compared/|first=Thomas|last=Soderstrom|title=Pipe Dreams: Six P35-DDR3 Motherboards Compared|date=2007-06-05|website=Tom's Hardware}}</ref> based on [[Intel Corporation|Intel]]'s [[Intel P35|P35 "Bearlake" chipset]] with DIMMs at bandwidths up to DDR3-1600 (PC3-12800).<ref>{{cite web|url=http://www.anandtech.com/printarticle.aspx?i=3045|first=Wesley|last=Fink|title=Super Talent & TEAM: DDR3-1600 Is Here!|date=2007-07-20|publisher=AnandTech}}</ref> The [[Intel Core i7]], released in November 2008, connects directly to memory rather than via a chipset. The Core i7, i5 & i3 CPUs initially supported only DDR3. [[Advanced Micro Devices|AMD]]'s [[socket AM3]] [[Phenom II]] X4 processors, released in February 2009, were their first to support DDR3 (while still supporting DDR2 for backwards compatibility).

===Dual-inline memory modules===
DDR3 [[DIMM|dual-inline memory modules (DIMMs)]] have 240 pins and are electrically incompatible with DDR2. A key notch—located differently in DDR2 and DDR3 DIMMs—prevents accidentally interchanging them. Not only are they keyed differently, but DDR2 has rounded notches on the side and the DDR3 modules have square notches on the side.<ref>{{cite web|title=Memory Module Picture 2007|author=DocMemory|date=2007-02-21|url=http://www.simmtester.com/page/news/showpubnews.asp?title=Memory+Module+Picture+2007&num=150|archive-url=https://web.archive.org/web/20170606080814/http://www.simmtester.com/page/news/showpubnews.asp?title=Memory+Module+Picture+2007&num=150|archive-date=2017-06-06|url-status=dead|access-date=2022-01-05}}</ref> DDR3 [[SO-DIMM]]s have 204 pins.<ref>{{Cite web|title=204-Pin DDR3 SDRAM unbuffered SODIMM design specification| publisher=JEDEC| date=May 2014| access-date=2015-07-05| url=https://www.jedec.org/standards-documents/docs/module-42018}}</ref>

For the [[Skylake microarchitecture]], Intel has also designed a SO-DIMM package named [[UniDIMM]], which can use either DDR3 or DDR4 chips. The CPU's integrated memory controller can then work with either. The purpose of UniDIMMs is to handle the transition from DDR3 to DDR4, where pricing and availability may make it desirable to switch RAM type. UniDIMMs have the same dimensions and number of pins as regular DDR4 SO-DIMMs, but the notch is placed differently to avoid accidentally using in an incompatible DDR4 SO-DIMM socket.<ref>{{cite web|url=http://www.techpowerup.com/205231/how-intel-plans-to-transition-between-ddr3-and-ddr4-for-the-mainstream.html|title=How Intel Plans to Transition Between DDR3 and DDR4 for the Mainstream|website=techpowerup.com|date=14 September 2014 |access-date=19 March 2018}}</ref>

===Latencies===
DDR3 latencies are numerically higher because the I/O bus [[Clock signal|clock]] cycles by which they are measured are shorter; the actual time interval is similar to DDR2 latencies, around 10&nbsp;ns. There is some improvement because DDR3 generally uses more recent manufacturing processes, but this is not directly caused by the change to DDR3.

CAS&nbsp;latency&nbsp;(ns) = 1000 × CL&nbsp;(cycles) ÷ clock&nbsp;frequency&nbsp;(MHz) = 2000 × CL&nbsp;(cycles) ÷ transfer&nbsp;rate&nbsp;(MT/s)

While the typical [[Memory timings|latencies]] for a JEDEC DDR2-800 device were 5-5-5-15 (12.5&nbsp;ns), some standard latencies for JEDEC DDR3 devices include 7-7-7-20 for DDR3-1066 (13.125&nbsp;ns) and 8-8-8-24 for DDR3-1333 (12&nbsp;ns).

As with earlier memory generations, faster DDR3 memory became available after the release of the initial versions. DDR3-2000 memory with 9-9-9-28 latency (9&nbsp;ns) was available in time to coincide with the Intel Core i7 release in late 2008,<ref>{{cite web |title=Kingston Rolls Out Industry's First 2GHz Memory Modules for Intel Core i7 Platforms |last=Shilov |first=Anton |date=2008-10-29 |access-date=2008-11-02 |publisher=Xbit Laboratories |url=http://www.xbitlabs.com/news/memory/display/20081029141143_Kingston_Rolls_Out_Industry_s_First_2GHz_Memory_Modules_for_Intel_Core_i7_Platforms.html |url-status=dead |archive-url=https://web.archive.org/web/20081101113745/http://www.xbitlabs.com/news/memory/display/20081029141143_Kingston_Rolls_Out_Industry_s_First_2GHz_Memory_Modules_for_Intel_Core_i7_Platforms.html |archive-date=2008-11-01 }}</ref> while later developments made DDR3-2400 widely available (with CL 9–12&nbsp;cycles = 7.5–10&nbsp;ns), and speeds up to DDR3-3200 available (with CL 13&nbsp;cycles = 8.125&nbsp;ns).

===Power consumption===
Power consumption of individual SDRAM chips (or, by extension, DIMMs) varies based on many factors, including speed, type of usage, voltage, etc. Dell's Power Advisor calculates that 4&nbsp;GB ECC DDR1333 RDIMMs use about 4&nbsp;W each.<ref>{{cite web |url=http://essa.us.dell.com/DellStarOnline/DCCP.aspx?c=us&l=en&s=corp&Template=6945c07e-3be7-47aa-b318-18f9052df893 |title=Dell Energy Smart Solution Advisor |publisher=Essa.us.dell.com |access-date=2013-07-28 |archive-url=https://web.archive.org/web/20130801070649/http://essa.us.dell.com/DellStarOnline/DCCP.aspx?c=us&l=en&s=corp&Template=6945c07e-3be7-47aa-b318-18f9052df893 |archive-date=2013-08-01 |url-status=dead }}</ref> By contrast, a more modern mainstream desktop-oriented part 8&nbsp;GB, DDR3/1600 DIMM, is rated at 2.58&nbsp;W, despite being significantly faster.<ref>http://www.kingston.com/dataSheets/KVR16N11_8.pdf {{Bare URL PDF|date=March 2022}}</ref>

===Modules===
{| class="wikitable sortable" style="text-align:left;"
|+List of standard DDR3 SDRAM modules
|-
! colspan="3" |Name
! colspan="2" |[[Chip (computing)|Chip]]
! colspan="3" |[[Bus (computing)|Bus]]
! colspan="2" |[[Memory timings|Timings]]
|-
!&nbsp;Standard
!Type
!&nbsp;Module
![[Clock rate]] {{Small|([[MHz]])}}
! Cycle time {{Small|([[Nanosecond|ns]])}}<ref>Cycle time is the inverse of the I/O bus clock frequency; e.g., 1/(100&nbsp;MHz) = 10&nbsp;ns per clock cycle.</ref>
! Clock rate {{Small|(MHz)}}
![[Transfer (computing)|Transfer rate]] {{Small|(MT/s)}}
![[Bandwidth (computing)|Bandwidth]] <small>([[MB/s]])</small>
! CL-T{{Sub|RCD}}-T{{Sub|RP}}
![[CAS latency]] {{Small|(ns)}}
|-
! rowspan="2" |DDR3-800
| D || rowspan="2" | PC3-6400 || rowspan="2" | 100 || rowspan="2" | 10 || rowspan="2" | 400 || rowspan="2" | 800 || rowspan="2" | 6400 || 5-5-5 || 12.5
|-
|E
|6-6-6
|15
|-
! rowspan="3" |DDR3-1066
| E || rowspan="3" | PC3-8500 || rowspan="3" | 133{{frac|1|3}} || rowspan="3" | 7{{frac|1|2}} || rowspan="3" | 533{{frac|1|3}} || rowspan="3" | 1066{{frac|2|3}} || rowspan="3" | 8533{{frac|1|3}} || 6-6-6 || 11.25
|-
|F
|7-7-7
|13.125
|-
|G
|8-8-8
|15
|-
! rowspan="4" |DDR3-1333
| F* || rowspan="4" | PC3-10600 || rowspan="4" | 166{{frac|2|3}} || rowspan="4" | 6 || rowspan="4" | 666{{frac|2|3}} || rowspan="4" | 1333{{frac|1|3}} || rowspan="4" | 10666{{frac|2|3}} || 7-7-7 || 10.5
|-
|G
|8-8-8
|12
|-
|H
|9-9-9
|13.5
|-
|J*
|10-10-10
|15
|-
! rowspan="4" |DDR3-1600
| G* || rowspan="4" | PC3-12800 || rowspan="4" | 200 || rowspan="4" | 5 || rowspan="4" | 800 || rowspan="4" | 1600 || rowspan="4" | 12800 || 8-8-8 || 10
|-
|H
|9-9-9
|11.25
|-
|J
|10-10-10
|12.5
|-
|K
|11-11-11
|13.75
|-
! rowspan=4 |DDR3-1866
| J* || rowspan=4 | PC3-14900 || rowspan=4 | 233{{frac|1|3}} || rowspan=4 | 4{{frac|2|7}} || rowspan=4 | 933{{frac|1|3}} || rowspan=4 | 1866{{frac|2|3}} || rowspan=4 | 14933{{frac|1|3}} || 10-10-10 || 10.56   
|-
|K
|11-11-11
|11.786
|-
|L
|12-12-12
|12.857
|-
|M*
|13-13-13
|13.929
|-
! rowspan=4 |DDR3-2133
| K* || rowspan=4 | PC3-17000 || rowspan=4 | 266{{frac|2|3}} || rowspan=4 | 3{{frac|3|4}} || rowspan=4 | 1066{{frac|2|3}} || rowspan=4 | 2133{{frac|1|3}} || rowspan=4 | 17066{{frac|2|3}} || 11-11-11 || 10.313
|-
|L
|12-12-12
|11.25
|-
|M
|13-13-13
|12.188
|-
|N*
|14-14-14
|13.125
|}
<nowiki>* optional</nowiki>

DDR3-xxx denotes data transfer rate, and describes DDR chips, whereas PC3-xxxx denotes theoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR3 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.

With two transfers per cycle of a quadrupled [[clock signal]], a 64-[[bit]] wide DDR3 module may achieve a transfer rate of up to 64 times the memory [[clock signal|clock]] speed. With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits in a byte). Thus with a memory clock frequency of 100&nbsp;MHz, DDR3 SDRAM gives a maximum transfer rate of 6400 [[MB/s]].

The data rate (in [[Transfer (computing)|MT/s]]) is twice the I/O bus clock (in [[MHz]]) due to the [[double data rate]] of DDR memory. As explained above, the bandwidth in MB/s is the data rate multiplied by eight.

CL – [[CAS Latency]] [[Clock signal|clock cycles]], between sending a column address to the memory and the beginning of the data in response

{{not a typo|tRCD}} – Clock cycles between row activate and reads/writes

{{not a typo|tRP}} – Clock cycles between row precharge and activate

Fractional frequencies are normally rounded down, but rounding up to 667 is common because of the exact number being 666{{frac|2|3}} and rounding to the nearest whole number. Some manufacturers also round to a certain precision or round up instead. For example, PC3-10666 memory could be listed as PC3-10600 or PC3-10700.<ref>{{citation|url=http://www.tomshardware.com/forum/274587-31-10600-10666-what-difference#t2045244 |title=Pc3 10600 vs. pc3 10666 What's the difference – New-System-Build |date=13 November 2009 |publisher=Tomshardware.com |access-date=2012-01-23}}</ref>

'''Note:''' All items listed above are specified by [[JEDEC]] as JESD79-3F.<ref name="JESD79-3F" />{{Rp|157–165}}All RAM data rates in-between or above these listed specifications are not standardized by JEDEC—often they are simply manufacturer optimizations using higher-tolerance or overvolted chips.  Of these non-standard specifications, the highest speeds would reach up to DDR3-3200.<ref>{{citation|url=https://bit-tech.net/news/tech/corsair-launches-fastest-ever-venegeance-pr/1/ |title=Corsair to offer fastest ever 3,200MHz Venegeance Pro DDR3 |publisher=bit-tech.net |date=2013-06-06 |access-date=2024-02-15}}</ref>

'''Alternative naming:''' DDR3 modules are often incorrectly labeled with the prefix PC (instead of PC3), for marketing reasons, followed by the data-rate. Under this convention PC3-10600 is listed as PC1333.<ref>{{citation|url=https://www.amazon.co.uk/Crucial-CT2KIT51264BA1339-PC1333-Memory-Retail/dp/B0036VO632 |title=Crucial Value CT2KIT51264BA1339 PC1333 4GB Memory RAM (DDR3, CL9) Retail  |publisher=www.amazon.co.uk |date=2016-05-10 |access-date=2016-05-10}}</ref>

===Serial presence detect===
DDR3 memory utilizes [[serial presence detect]].<ref name="spd">{{cite web | url=https://www.simmtester.com/News/PublicationArticle/153 | title=Understanding DDR3 Serial Presence Detect (SPD) Table | publisher=simmtester.com | access-date=12 December 2015}}</ref> Serial presence detect (SPD) is a standardized way to automatically access information about a [[random-access memory|computer memory module]], using a serial interface. It is typically used during the [[power-on self-test]] for automatic configuration of memory modules.

====Release 4====
Release 4 of the DDR3 [[Serial presence detect|Serial Presence Detect]] (SPD) document (SPD4_01_02_11) adds support for Load Reduction DIMMs and also for 16b-SO-DIMMs and 32b-SO-DIMMs.

JEDEC Solid State Technology Association announced the publication of Release 4 of the DDR3 Serial Presence Detect (SPD) document on September 1, 2011.<ref>{{cite web|title=JEDEC Announces Publication of Release 4 of the DDR3 Serial Presence Detect Specification|url=http://www.jedec.org/news/pressreleases/jedec-announces-publication-release-4-ddr3-serial-presence-detect-specification}}</ref>

====XMP extension====
Intel Corporation officially introduced the eXtreme Memory Profile ([[Serial presence detect#Intel Extreme Memory Profile (XMP)|XMP]]) Specification on March 23, 2007, to enable enthusiast performance extensions to the traditional JEDEC [[Serial Presence Detect|SPD]] specifications for DDR3 SDRAM.<ref>{{cite web|title=Intel Extreme memory Profile (Intel XMP) DDR3 Technology|url=http://www.intel.com/assets/pdf/whitepaper/319124.pdf|access-date=2009-05-29}}</ref>

==Variants==
In addition to bandwidth designations (e.g. DDR3-800D), and capacity variants, modules can be one of the following:
# [[ECC memory]], which has an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional '''ECC''' or '''E''' in their designation. For example: "PC3-6400 ECC", or PC3-8500E.<ref>{{citation|url=http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf|publisher=Hewlett-Packard|title=Memory technology evolution: an overview of system memory technologies|page=18|url-status=dead|archive-url=https://web.archive.org/web/20110724013507/http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf|archive-date=2011-07-24}}</ref>
# [[Registered memory|Registered or buffered memory]], which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals with a [[hardware register|register]], at a cost of an extra clock of increased latency. Those modules are identified by an additional '''R''' in their designation, for example PC3-6400R.<ref name="simmtester.com">{{cite web
 | url = http://www.simmtester.com/page/news/showpubnews.asp?num=167
 | title = What is LR-DIMM, LRDIMM Memory? (Load-Reduce DIMM)
 | access-date = 2014-08-29
 | website = simmtester.com
 | archive-date = 2014-09-03
 | archive-url = https://web.archive.org/web/20140903094720/http://www.simmtester.com/page/news/showpubnews.asp?num=167
 | url-status = dead
 }}</ref>
# Non-registered (a.k.a. "[[Unbuffered memory|unbuffered]]") RAM ''may  be'' identified by an additional '''U''' in the designation.<ref name="simmtester.com" /> 
# [[Fully Buffered DIMM|Fully buffered]] modules, which are designated by '''F''' or '''FB''' and do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.
# [[LRDIMM|Load reduced]] modules, which are designated by '''LR''' and are similar to registered/buffered memory, in a way that LRDIMM modules buffer both control and data lines while retaining the parallel nature of all signals. As such, LRDIMM memory provides large overall maximum memory capacities, while addressing some of the performance and power consumption issues of '''FB''' memory induced by the required conversion between serial and parallel signal forms.

Both FBDIMM (fully buffered) and LRDIMM (load reduced) memory types are designed primarily to control the amount of electric current flowing to and from the memory chips at any given time. They are not compatible with registered/buffered memory, and motherboards that require them usually will not accept any other kind of memory.

=== {{Anchor|DDR3L|DDR3U}}DDR3L and DDR3U extensions ===
The '''DDR3L''' ('''DDR3 L'''ow Voltage) standard is an addendum to the JESD79-3 DDR3 Memory Device Standard specifying low voltage devices.<ref name="jedecddr3l">{{cite web|url=https://www.jedec.org/standards-documents/docs/jesd79-3-1a01|title=Addendum No. 1 to JESD79-3 – 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866|date=May 2013|access-date=2019-09-08}}</ref> The DDR3L standard is 1.35&nbsp;V and has the label ''PC3L'' for its modules. Examples include DDR3L‐800 (PC3L-6400), DDR3L‐1066 (PC3L-8500), DDR3L‐1333 (PC3L-10600), and DDR3L‐1600 (PC3L-12800). Memory specified to DDR3L and DDR3U specifications is compatible with the original DDR3 standard, and can run at either the lower voltage or at 1.50 V.<ref>{{cite web|url=https://www.jedec.org/standards-documents/docs/jesd79-3-1a01|title=Addendum No. 1 to JESD79-3 – 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866|date=May 2013|url-access=registration|access-date=2019-09-08|quote=DDR3L VDD/VDDQ requirements – Power Supply: DDR3L operation = 1.283 V to 1.45 V; DDR3 operation = 1.425 V to 1.575 V .. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3 operation}}</ref> However, devices that require DDR3L explicitly, which operate at 1.35&nbsp;V, such as systems using mobile versions of fourth-generation Intel Core processors, are not compatible with 1.50&nbsp;V DDR3 memory.<ref>{{cite web|title=What is DDR3L Memory?|url=http://www.dell.com/support/article/us/en/19/SLN153768/EN|website=Dell.com|publisher=[[Dell]]|date=2016-10-03|access-date=2016-10-04}}</ref> DDR3L is different from and incompatible with the [[LPDDR#LP-DDR3|LPDDR3]] mobile memory standard.

The '''DDR3U''' ('''DDR3 U'''ltra Low Voltage) standard is 1.25&nbsp;V and has the label ''PC3U'' for its modules.<ref>{{cite web|url=https://www.jedec.org/standards-documents/docs/jesd79-3-2|title=Addendum No. 2 to JESD79-3, 1.25 V DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600|date=October 2011|access-date=2019-09-08}}</ref>

JEDEC Solid State Technology Association announced the publication of JEDEC DDR3L on July 26, 2010<ref>{{cite web|title=Specification Will Encourage Lower Power Consumption for Countless Consumer Electronics, Networking and Computer Products|url=http://www.jedec.org/news/pressreleases/jedec-publishes-widely-anticipated-ddr3l-low-voltage-memory-standard}}</ref> and the DDR3U in October 2011.<ref>{{cite web|title=Addendum No. 2 to JESD79-3, 1.25 V DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600|url=https://www.jedec.org/category/keywords/ddr3u}}</ref>

==Feature summary==

===Components===
* Introduction of asynchronous RESET pin
* Support of system-level flight-time compensation
* On-[[DIMM]] mirror-friendly DRAM pinout
* Introduction of CWL (CAS write latency) per clock bin
* On-die I/O calibration engine
* READ and WRITE calibration
* Dynamic ODT (On-Die-Termination) feature allows different termination values for Reads and Writes

===Modules===
* Fly-by command/address/control bus with on-DIMM termination
* High-precision calibration resistors
* Are '''not''' [[Backward compatibility|backwards compatible]]—DDR3 modules do not fit into DDR2 sockets; forcing them can damage the DIMM and/or the motherboard<ref>{{cite web
 |url         = http://www.kingston.com/channelmarketingcenter/hyperx/literature/MKF_1223_DDR3_FAQ.pdf
 |title       = DDR3: Frequently Asked Questions
 |access-date  = 2009-08-18
 |url-status     = dead
 |archive-url  = https://web.archive.org/web/20091229190303/http://www.kingston.com/channelmarketingcenter/hyperx/literature/MKF_1223_DDR3_FAQ.pdf
 |archive-date = 2009-12-29
}}</ref>

===Technological advantages over DDR2===
* Higher bandwidth performance, up to 2133 MT/s standardized
* Slightly improved latencies, as measured in nanoseconds
* Higher performance at low power (longer battery life in laptops)
* Enhanced low-power features

== See also ==
* [[List of interface bit rates]]
* [[LPDDR#LPDDR3|Low power DDR3 SDRAM]] (LPDDR3)
* [[Multi-channel memory architecture]]

== Notes ==
{{Notelist}}

== References ==
{{Reflist}}

== External links ==
* JEDEC standard No. 79-3 (JESD79-3: DDR3 SDRAM)
**[https://www.jedec.org/standards-documents/docs/jesd-79-3d DDR3 SDRAM standard JESD79-3F]
**[https://www.jedec.org/standards-documents/docs/jesd79-3-1a01 Addendum No. 1 to JESD79-3 – 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866 (JESD79-3-1A.01)]
**[https://www.jedec.org/standards-documents/docs/jesd79-3-2 Addendum No. 2 to JESD79-3 – 1.25 V DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600]
**[https://www.jedec.org/standards-documents/docs/jesd79-3-3-0 Addendum No. 3 to JESD79-3 – 3D Stacked SDRAM]
* SPD (Serial Presence Detect), from JEDEC standard No. 21-C (JESD21C: JEDEC configurations for solid state memories)
**[http://www.jedec.org/standards-documents/docs/spd-4010211 SPD Annex K – Serial Presence Detect (SPD) for DDR3 SDRAM Modules (SPD4_01_02_11)]
* [http://start-test.com/Products/JTAGExternalModules.php DDR, DDR2, DDR3 memory slots testing]
* [https://courses.cs.washington.edu/courses/cse467/11wi/lectures/SDRAM.pdf DDR3 Synchronous DRAM Memory]

{{DRAM}}

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[[Category:SDRAM]]

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